113 lines
3.4 KiB
C
113 lines
3.4 KiB
C
/*
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* Copyright 2020 Broadcom
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef DMA_IPROC_PAX_V1
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#define DMA_IPROC_PAX_V1
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#include "dma_iproc_pax.h"
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/* Register RM_CONTROL fields */
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#define RM_COMM_MSI_INTERRUPT_STATUS_MASK 0x30d0
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#define RM_COMM_MSI_INTERRUPT_STATUS_CLEAR 0x30d4
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#define RM_COMM_CONTROL_MODE_MASK 0x3
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#define RM_COMM_CONTROL_MODE_SHIFT 0
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#define RM_COMM_CONTROL_MODE_TOGGLE 0x2
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#define RM_COMM_CONTROL_CONFIG_DONE BIT(2)
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#define RM_COMM_CONTROL_LINE_INTR_EN_SHIFT 4
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#define RM_COMM_CONTROL_LINE_INTR_EN BIT(4)
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#define RM_COMM_CONTROL_AE_TIMEOUT_EN_SHIFT 5
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#define RM_COMM_CONTROL_AE_TIMEOUT_EN BIT(5)
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#define RM_COMM_MSI_DISABLE_VAL 3
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#define PAX_DMA_TYPE_DMA_DESC 0x3
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#define PAX_DMA_NUM_BD_BUFFS 8
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/* DMA desc count: 3 entries per packet */
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#define PAX_DMA_RM_DESC_BDCOUNT 3
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/* 1 DMA packet desc takes 3 BDs */
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#define PAX_DMA_DMA_DESC_SIZE (PAX_DMA_RM_DESC_BDWIDTH * \
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PAX_DMA_RM_DESC_BDCOUNT)
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/* Max size of transfer in single packet */
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#define PAX_DMA_MAX_DMA_SIZE_PER_BD (16 * 1024 * 1024)
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/* ascii signature 'V' 'K' */
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#define PAX_DMA_WRITE_SYNC_SIGNATURE 0x564B
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/* DMA transfers supported from 4 bytes thru 16M, size aligned to 4 bytes */
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#define PAX_DMA_MIN_SIZE 4
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#define PAX_DMA_MAX_SIZE (16 * 1024 * 1024)
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/* Bits 0:1 ignored by PAX DMA, i.e. 4-byte address alignment */
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#define PAX_DMA_PCI_ADDR_LS_IGNORE_BITS 2
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#define PAX_DMA_PCI_ADDR_ALIGNMT_SHIFT PAX_DMA_PCI_ADDR_LS_IGNORE_BITS
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/* s/w payload struct, enough space for 1020 sglist elements */
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#define PAX_DMA_PAYLOAD_BUFF_SIZE (32 * 1024)
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/*
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* Per-ring memory, with 8K & 4K alignment
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* Alignment may not be ensured by allocator
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* s/w need to allocate extra upto 8K to
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* ensure aligned memory space.
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*/
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#define PAX_DMA_PER_RING_ALLOC_SIZE (PAX_DMA_RM_CMPL_RING_SIZE * 2 + \
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PAX_DMA_NUM_BD_BUFFS * \
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PAX_DMA_RM_DESC_RING_SIZE + \
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PAX_DMA_PAYLOAD_BUFF_SIZE)
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/* RM header desc field */
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struct rm_header {
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uint64_t opq : 16; /*pkt_id 15:0*/
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uint64_t res1 : 20; /*reserved 35:16*/
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uint64_t bdcount : 5; /*bdcount 40:36*/
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uint64_t prot : 2; /*prot 41:40*/
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uint64_t res2 : 13; /*reserved 55:43*/
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uint64_t start : 1; /*start pkt :56*/
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uint64_t end : 1; /*end pkt :57*/
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uint64_t toggle : 1; /*toggle :58*/
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uint64_t res3 : 1; /*reserved :59*/
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uint64_t type : 4; /*type 63:60*/
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} __attribute__ ((__packed__));
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/* dma desc header field */
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struct dma_header_desc {
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uint64_t length : 25; /*transfer length in bytes 24:0*/
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uint64_t res1: 31; /*reserved 55:25*/
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uint64_t opcode : 4; /*opcode 59:56*/
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uint64_t res2: 2; /*reserved 61:60*/
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uint64_t type : 2; /*type 63:62 set to b'11*/
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} __attribute__ ((__packed__));
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/* dma desc AXI addr field */
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struct axi_addr_desc {
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uint64_t axi_addr : 48; /*axi_addr[47:0]*/
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uint64_t res : 14; /*reserved 48:61*/
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uint64_t type : 2; /*63:62 set to b'11*/
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} __attribute__ ((__packed__));
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/* dma desc PCI addr field */
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struct pci_addr_desc {
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uint64_t pcie_addr : 62; /*pcie_addr[63:2]*/
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uint64_t type : 2; /*63:62 set to b'11*/
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} __attribute__ ((__packed__));
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/* DMA descriptor */
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struct dma_desc {
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struct dma_header_desc hdr;
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struct axi_addr_desc axi;
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struct pci_addr_desc pci;
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} __attribute__ ((__packed__));
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struct next_ptr_desc {
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uint64_t addr : 44; /*Address 43:0*/
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uint64_t res1 : 14;/*Reserved*/
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uint64_t toggle : 1; /*Toggle Bit:58*/
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uint64_t res2 : 1;/*Reserved 59:59*/
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uint64_t type : 4;/*descriptor type 63:60*/
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} __attribute__ ((__packed__));
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#endif
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