155 lines
6.3 KiB
C
155 lines
6.3 KiB
C
/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_CODEC_WM8904_H_
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#define ZEPHYR_INCLUDE_CODEC_WM8904_H_
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define WM8904_REG_RESET (0x00)
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#define WM8904_REG_ANALOG_ADC_0 (0x0A)
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#define WM8904_REG_POWER_MGMT_0 (0x0C)
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#define WM8904_REG_POWER_MGMT_2 (0x0E)
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#define WM8904_REG_POWER_MGMT_3 (0x0F)
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#define WM8904_REG_POWER_MGMT_6 (0x12)
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#define WM8904_REG_CLK_RATES_0 (0x14)
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#define WM8904_REG_CLK_RATES_1 (0x15)
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#define WM8904_REG_CLK_RATES_2 (0x16)
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#define WM8904_REG_AUDIO_IF_0 (0x18)
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#define WM8904_REG_AUDIO_IF_1 (0x19)
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#define WM8904_REG_AUDIO_IF_2 (0x1A)
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#define WM8904_REG_AUDIO_IF_3 (0x1B)
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#define WM8904_REG_DAC_DIG_1 (0x21)
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#define WM8904_REG_DAC_DIG_0 (0x27)
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#define WM8904_REG_ANALOG_LEFT_IN_0 (0x2C)
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#define WM8904_REG_ANALOG_RIGHT_IN_0 (0x2D)
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#define WM8904_REG_ANALOG_LEFT_IN_1 (0x2E)
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#define WM8904_REG_ANALOG_RIGHT_IN_1 (0x2F)
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#define WM8904_REG_ANALOG_OUT1_LEFT (0x39)
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#define WM8904_REG_ANALOG_OUT1_RIGHT (0x3A)
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#define WM8904_REG_ANALOG_OUT12_ZC (0x3D)
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#define WM8904_REG_DC_SERVO_0 (0x43)
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#define WM8904_REG_ANALOG_HP_0 (0x5A)
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#define WM8904_REG_CHRG_PUMP_0 (0x62)
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#define WM8904_REG_CLS_W_0 (0x68)
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#define WM8904_REG_WRT_SEQUENCER_0 (0x6C)
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#define WM8904_REG_WRT_SEQUENCER_3 (0x6F)
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#define WM8904_REG_WRT_SEQUENCER_4 (0x70)
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#define WM8904_REG_DAC_DIGITAL_VOLUME_LEFT (0x1E)
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#define WM8904_REG_DAC_DIGITAL_VOLUME_RIGHT (0x1F)
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#define WM8904_REG_ADC_DIGITAL_VOLUME_LEFT (0x24)
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#define WM8904_REG_ADC_DIGITAL_VOLUME_RIGHT (0x25)
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#define WM8904_REG_ANALOG_OUT2_LEFT (0x3B)
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#define WM8904_REG_ANALOG_OUT2_RIGHT (0x3C)
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#define WM8904_REG_GPIO_CONTROL_4 (0x7C)
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/* FLL control register */
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#define WM8904_REG_FLL_CONTROL_1 (0x74)
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#define WM8904_REG_FLL_CONTROL_2 (0x75)
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#define WM8904_REG_FLL_CONTROL_3 (0x76)
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#define WM8904_REG_FLL_CONTROL_4 (0x77)
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#define WM8904_REG_FLL_CONTROL_5 (0x78)
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/* GPIO control register */
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#define WM8904_REG_GPIO_CONTROL_1 (0x79)
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#define WM8904_REG_GPIO_CONTROL_2 (0x7A)
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#define WM8904_REG_GPIO_CONTROL_3 (0x7B)
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#define WM8904_REG_GPIO_CONTROL_4 (0x7C)
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/* fll nco */
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#define WM8904_REG_FLL_NCO_TEST_0 (0xF7U)
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#define WM8904_REG_FLL_NCO_TEST_1 (0xF8U)
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#define WM8904_OUTPUT_VOLUME_MIN (0b000000)
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#define WM8904_OUTPUT_VOLUME_MAX (0b111111)
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#define WM8904_OUTPUT_VOLUME_DEFAULT (0b101101)
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#define WM8904_INPUT_VOLUME_MIN (0b00000)
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#define WM8904_INPUT_VOLUME_MAX (0b11111)
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#define WM8904_INPUT_VOLUME_DEFAULT (0b00101)
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/**
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* WM8904_ANALOG_OUT1_LEFT, WM8904_ANALOG_OUT1_RIGHT (headphone outs),
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* WM8904_ANALOG_OUT2_LEFT, WM8904_ANALOG_OUT2_RIGHT (line outs):
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* [8] - MUTE: Output mute
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* [7] - VU: Volume update, works for entire channel pair
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* [6] - ZC: Zero-crossing enable
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* [5:0] - VOL: 6-bit volume value
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*/
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#define WM8904_REGVAL_OUT_VOL(mute, vu, zc, vol) \
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(((mute & 0b1) << 8) | (vu & 0b1) << 7 | (zc & 0b1) << 6 | (vol & 0b000111111))
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#define WM8904_REGMASK_OUT_MUTE 0b100000000
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#define WM8904_REGMASK_OUT_VU 0b010000000
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#define WM8904_REGMASK_OUT_ZC 0b001000000
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#define WM8904_REGMASK_OUT_VOL 0b000111111
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/**
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* WM8904_ANALOG_LEFT_IN_0, WM8904_ANALOG_RIGHT_IN_0:
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* [7] - MUTE: Input mute
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* [4:0] - VOL: 5 bit volume value
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*/
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#define WM8904_REGVAL_IN_VOL(mute, vol) \
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((mute & 0b1) << 7 | (vol & 0b00011111))
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#define WM8904_REGMASK_IN_MUTE 0b10000000
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#define WM8904_REGMASK_IN_VOLUME 0b00011111
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/**
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* WM8904_ANALOG_LEFT_IN_1, WM8904_ANALOG_RIGHT_IN_1:
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* [6] - INx_CM_ENA: Common-mode rejection enable (N/A for single-mode)
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* [5:4] - x_IP_SEL_N: Inverting input selection
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* [3:2] - x_IP_SEL_P: Non-inverting input selection
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* [1:0] - x_MODE: Input mode
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*/
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#define WM8904_REGVAL_INSEL(cm, nin, pin, mode) \
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(((cm) & 0b1) << 6) | (((nin) & 0b11) << 4)
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#define WM8904_REGMASK_INSEL_CMENA 0b01000000
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#define WM8904_REGMASK_INSEL_IP_SEL_N 0b00110000
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#define WM8904_REGMASK_INSEL_IP_SEL_P 0b00001100
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#define WM8904_REGMASK_INSEL_MODE 0b00000011
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/*!@brief WM8904 maximum volume */
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#define WM8904_MAP_HEADPHONE_LINEOUT_MAX_VOLUME 0x3FU
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#define WM8904_DAC_MAX_VOLUME 0xC0U
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/*! @brief The audio data transfer protocol. */
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typedef enum _wm8904_protocol {
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kWM8904_ProtocolI2S = 0x2, /*!< I2S type */
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kWM8904_ProtocolLeftJustified = 0x1, /*!< Left justified mode */
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kWM8904_ProtocolRightJustified = 0x0, /*!< Right justified mode */
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kWM8904_ProtocolPCMA = 0x3, /*!< PCM A mode */
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kWM8904_ProtocolPCMB = 0x3 | (1 << 4), /*!< PCM B mode */
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} wm8904_protocol_t;
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/*! @brief The SYSCLK / fs ratio. */
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typedef enum _wm8904_fs_ratio {
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kWM8904_FsRatio64X = 0x0, /*!< SYSCLK is 64 * sample rate * frame width */
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kWM8904_FsRatio128X = 0x1, /*!< SYSCLK is 128 * sample rate * frame width */
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kWM8904_FsRatio192X = 0x2, /*!< SYSCLK is 192 * sample rate * frame width */
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kWM8904_FsRatio256X = 0x3, /*!< SYSCLK is 256 * sample rate * frame width */
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kWM8904_FsRatio384X = 0x4, /*!< SYSCLK is 384 * sample rate * frame width */
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kWM8904_FsRatio512X = 0x5, /*!< SYSCLK is 512 * sample rate * frame width */
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kWM8904_FsRatio768X = 0x6, /*!< SYSCLK is 768 * sample rate * frame width */
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kWM8904_FsRatio1024X = 0x7, /*!< SYSCLK is 1024 * sample rate * frame width */
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kWM8904_FsRatio1408X = 0x8, /*!< SYSCLK is 1408 * sample rate * frame width */
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kWM8904_FsRatio1536X = 0x9 /*!< SYSCLK is 1536 * sample rate * frame width */
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} wm8904_fs_ratio_t;
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/*! @brief Sample rate. */
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typedef enum _wm8904_sample_rate {
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kWM8904_SampleRate8kHz = 0x0, /*!< 8 kHz */
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kWM8904_SampleRate12kHz = 0x1, /*!< 12kHz */
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kWM8904_SampleRate16kHz = 0x2, /*!< 16kHz */
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kWM8904_SampleRate24kHz = 0x3, /*!< 24kHz */
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kWM8904_SampleRate32kHz = 0x4, /*!< 32kHz */
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kWM8904_SampleRate48kHz = 0x5, /*!< 48kHz */
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kWM8904_SampleRate11025Hz = 0x6, /*!< 11.025kHz */
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kWM8904_SampleRate22050Hz = 0x7, /*!< 22.05kHz */
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kWM8904_SampleRate44100Hz = 0x8 /*!< 44.1kHz */
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} wm8904_sample_rate_t;
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#endif /* ZEPHYR_INCLUDE_CODEC_WM8904_H_ */
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