333 lines
8.5 KiB
C
333 lines
8.5 KiB
C
/*
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* Copyright (c) 2023 Caspar Friedrich <c.s.w.friedrich@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/adc.h>
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#include <zephyr/drivers/i2c.h>
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/sys/byteorder.h>
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#define ADC_CONTEXT_USES_KERNEL_TIMER
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/*
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* This requires to be included _after_ `#define ADC_CONTEXT_USES_KERNEL_TIMER`
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*/
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#include "adc_context.h"
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#define DT_DRV_COMPAT ti_tla2021
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LOG_MODULE_REGISTER(tla2021, CONFIG_ADC_LOG_LEVEL);
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#define ACQ_THREAD_PRIORITY CONFIG_ADC_TLA2021_ACQUISITION_THREAD_PRIORITY
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#define ACQ_THREAD_STACK_SIZE CONFIG_ADC_TLA2021_ACQUISITION_THREAD_STACK_SIZE
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#define ADC_CHANNEL_msk BIT(0)
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#define ADC_RESOLUTION 12
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/*
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* Conversion Data Register (RP = 00h) [reset = 0000h]
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*/
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#define REG_DATA 0x00
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#define REG_DATA_pos 4
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/*
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* Configuration Register (RP = 01h) [reset = 8583h]
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*/
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#define REG_CONFIG 0x01
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#define REG_CONFIG_DEFAULT 0x8583
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#define REG_CONFIG_DR_pos 5
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#define REG_CONFIG_MODE_pos 8
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#define REG_CONFIG_PGA_pos 9 /* TLA2022 and TLA2024 Only */
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#define REG_CONFIG_MUX_pos 12 /* TLA2024 Only */
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#define REG_CONFIG_OS_pos 15
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#define REG_CONFIG_OS_msk (BIT_MASK(1) << REG_CONFIG_OS_pos)
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typedef int16_t tla2021_reg_data_t;
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typedef uint16_t tla2021_reg_config_t;
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struct tla2021_config {
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const struct i2c_dt_spec bus;
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};
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struct tla2021_data {
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const struct device *dev;
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struct adc_context ctx;
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#ifdef CONFIG_ADC_ASYNC
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struct k_sem acq_lock;
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#endif
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tla2021_reg_data_t *buffer;
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tla2021_reg_data_t *repeat_buffer;
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/*
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* Shadow register
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*/
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tla2021_reg_config_t reg_config;
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};
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static int tla2021_read_register(const struct device *dev, uint8_t reg, uint16_t *value)
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{
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int ret;
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const struct tla2021_config *config = dev->config;
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uint8_t tmp[2];
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ret = i2c_write_read_dt(&config->bus, ®, sizeof(reg), tmp, sizeof(tmp));
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if (ret) {
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return ret;
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}
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*value = sys_get_be16(tmp);
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return 0;
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}
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static int tla2021_write_register(const struct device *dev, uint8_t reg, uint16_t value)
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{
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int ret;
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const struct tla2021_config *config = dev->config;
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uint8_t tmp[3] = {reg};
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sys_put_be16(value, &tmp[1]);
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ret = i2c_write_dt(&config->bus, tmp, sizeof(tmp));
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if (ret) {
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return ret;
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}
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return 0;
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}
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static int tla2021_channel_setup(const struct device *dev, const struct adc_channel_cfg *cfg)
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{
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if (cfg->gain != ADC_GAIN_1) {
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LOG_ERR("Invalid gain");
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return -EINVAL;
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}
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if (cfg->reference != ADC_REF_INTERNAL) {
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LOG_ERR("Invalid reference");
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return -EINVAL;
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}
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if (cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
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LOG_ERR("Invalid acquisition time");
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return -EINVAL;
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}
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return 0;
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}
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static int tla2021_start_read(const struct device *dev, const struct adc_sequence *seq)
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{
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struct tla2021_data *data = dev->data;
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const size_t num_extra_samples = seq->options ? seq->options->extra_samplings : 0;
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const size_t num_samples = (1 + num_extra_samples) * POPCOUNT(seq->channels);
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if (!(seq->channels & ADC_CHANNEL_msk)) {
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LOG_ERR("Selected channel(s) not supported: %x", seq->channels);
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return -EINVAL;
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}
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if (seq->resolution != ADC_RESOLUTION) {
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LOG_ERR("Selected resolution not supported: %d", seq->resolution);
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return -EINVAL;
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}
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if (seq->oversampling) {
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LOG_ERR("Oversampling is not supported");
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return -EINVAL;
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}
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if (seq->calibrate) {
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LOG_ERR("Calibration is not supported");
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return -EINVAL;
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}
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if (!seq->buffer) {
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LOG_ERR("Buffer invalid");
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return -EINVAL;
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}
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if (seq->buffer_size < (num_samples * sizeof(tla2021_reg_data_t))) {
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LOG_ERR("buffer size too small");
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return -EINVAL;
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}
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data->buffer = seq->buffer;
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adc_context_start_read(&data->ctx, seq);
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return adc_context_wait_for_completion(&data->ctx);
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}
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static int tla2021_read_async(const struct device *dev, const struct adc_sequence *seq,
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struct k_poll_signal *async)
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{
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int ret;
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struct tla2021_data *data = dev->data;
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adc_context_lock(&data->ctx, async ? true : false, async);
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ret = tla2021_start_read(dev, seq);
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adc_context_release(&data->ctx, ret);
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return ret;
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}
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static int tla2021_read(const struct device *dev, const struct adc_sequence *seq)
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{
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return tla2021_read_async(dev, seq, NULL);
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}
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static void tla2021_perform_read(const struct device *dev)
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{
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struct tla2021_data *data = dev->data;
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tla2021_reg_config_t reg;
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tla2021_reg_data_t res;
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int ret;
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/*
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* Wait until sampling is done
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*/
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do {
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ret = tla2021_read_register(dev, REG_CONFIG, ®);
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if (ret < 0) {
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adc_context_complete(&data->ctx, ret);
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}
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} while (!(reg & REG_CONFIG_OS_msk));
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/*
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* Read result
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*/
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ret = tla2021_read_register(dev, REG_DATA, &res);
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if (ret) {
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adc_context_complete(&data->ctx, ret);
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}
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/*
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* ADC data is stored in the upper 12 bits
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*/
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res >>= REG_DATA_pos;
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*data->buffer++ = res;
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adc_context_on_sampling_done(&data->ctx, data->dev);
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}
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static void adc_context_start_sampling(struct adc_context *ctx)
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{
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int ret;
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struct tla2021_data *data = CONTAINER_OF(ctx, struct tla2021_data, ctx);
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const struct device *dev = data->dev;
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tla2021_reg_config_t reg = data->reg_config;
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/*
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* Start single-shot conversion
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*/
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WRITE_BIT(reg, REG_CONFIG_MODE_pos, 1);
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WRITE_BIT(reg, REG_CONFIG_OS_pos, 1);
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ret = tla2021_write_register(dev, REG_CONFIG, reg);
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if (ret) {
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LOG_WRN("Failed to start conversion");
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}
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data->repeat_buffer = data->buffer;
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#ifdef CONFIG_ADC_ASYNC
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k_sem_give(&data->acq_lock);
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#else
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tla2021_perform_read(dev);
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#endif
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}
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static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
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{
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struct tla2021_data *data = CONTAINER_OF(ctx, struct tla2021_data, ctx);
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if (repeat_sampling) {
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data->buffer = data->repeat_buffer;
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}
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}
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#ifdef CONFIG_ADC_ASYNC
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static void tla2021_acq_thread_fn(void *p1, void *p2, void *p3)
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{
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const struct device *dev = p1;
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struct tla2021_data *data = dev->data;
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while (true) {
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k_sem_take(&data->acq_lock, K_FOREVER);
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tla2021_perform_read(dev);
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}
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}
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#endif
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static int tla2021_init(const struct device *dev)
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{
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int ret;
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const struct tla2021_config *config = dev->config;
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struct tla2021_data *data = dev->data;
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if (!i2c_is_ready_dt(&config->bus)) {
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LOG_ERR("Bus not ready");
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return -EINVAL;
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}
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ret = tla2021_write_register(dev, REG_CONFIG, data->reg_config);
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if (ret) {
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LOG_ERR("Device reset failed: %d", ret);
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return ret;
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}
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adc_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static const struct adc_driver_api tla2021_driver_api = {
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.channel_setup = tla2021_channel_setup,
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.read = tla2021_read,
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.ref_internal = 4096,
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#ifdef CONFIG_ADC_ASYNC
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.read_async = tla2021_read_async,
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#endif
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};
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#define TLA2021_THREAD_INIT(n) \
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K_THREAD_DEFINE(adc_tla2021_##n##_thread, ACQ_THREAD_STACK_SIZE, tla2021_acq_thread_fn, \
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DEVICE_DT_INST_GET(n), NULL, NULL, ACQ_THREAD_PRIORITY, 0, 0);
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#define TLA2021_INIT(n) \
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static const struct tla2021_config inst_##n##_config; \
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static struct tla2021_data inst_##n##_data; \
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IF_ENABLED(CONFIG_ADC_ASYNC, (TLA2021_THREAD_INIT(n))) \
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static const struct tla2021_config inst_##n##_config = { \
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.bus = I2C_DT_SPEC_INST_GET(n), \
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}; \
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static struct tla2021_data inst_##n##_data = { \
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.dev = DEVICE_DT_INST_GET(n), \
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ADC_CONTEXT_INIT_LOCK(inst_##n##_data, ctx), \
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ADC_CONTEXT_INIT_TIMER(inst_##n##_data, ctx), \
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ADC_CONTEXT_INIT_SYNC(inst_##n##_data, ctx), \
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.reg_config = REG_CONFIG_DEFAULT, \
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IF_ENABLED(CONFIG_ADC_ASYNC, \
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(.acq_lock = Z_SEM_INITIALIZER(inst_##n##_data.acq_lock, 0, 1),)) \
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}; \
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DEVICE_DT_INST_DEFINE(n, &tla2021_init, NULL, &inst_##n##_data, &inst_##n##_config, \
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POST_KERNEL, CONFIG_ADC_TLA2021_INIT_PRIORITY, &tla2021_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(TLA2021_INIT)
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BUILD_ASSERT(CONFIG_I2C_INIT_PRIORITY < CONFIG_ADC_TLA2021_INIT_PRIORITY);
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