508 lines
13 KiB
C
508 lines
13 KiB
C
/*
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* Copyright (c) 2022 BrainCo Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT gd_gd32_adc
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#include <errno.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/gd32.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/adc.h>
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#include <zephyr/drivers/reset.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/irq.h>
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#include <gd32_adc.h>
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#include <gd32_rcu.h>
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#define ADC_CONTEXT_USES_KERNEL_TIMER
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#include "adc_context.h"
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(adc_gd32, CONFIG_ADC_LOG_LEVEL);
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/**
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* @brief gd32 adc irq have some special cases as below:
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* 1. adc number no larger than 3.
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* 2. adc0 and adc1 share the same irq number.
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* 3. For gd32f4xx, adc2 share the same irq number with adc0 and adc1.
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*
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* To cover this cases, gd32_adc driver use node-label 'adc0', 'adc1' and
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* 'adc2' to handle gd32 adc irq config directly.'
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*
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* @note Sorry for the restriction, But new added gd32 adc node-label must be 'adc0',
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* 'adc1' and 'adc2'.
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*/
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#define ADC0_NODE DT_NODELABEL(adc0)
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#define ADC1_NODE DT_NODELABEL(adc1)
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#define ADC2_NODE DT_NODELABEL(adc2)
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#define ADC0_ENABLE DT_NODE_HAS_STATUS_OKAY(ADC0_NODE)
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#define ADC1_ENABLE DT_NODE_HAS_STATUS_OKAY(ADC1_NODE)
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#define ADC2_ENABLE DT_NODE_HAS_STATUS_OKAY(ADC2_NODE)
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#ifndef ADC0
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/**
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* @brief The name of gd32 ADC HAL are different between single and multi ADC SoCs.
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* This adjust the single ADC SoC HAL, so we can call gd32 ADC HAL in a common way.
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*/
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#undef ADC_STAT
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#undef ADC_CTL0
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#undef ADC_CTL1
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#undef ADC_SAMPT0
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#undef ADC_SAMPT1
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#undef ADC_RSQ2
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#undef ADC_RDATA
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#define ADC_STAT(adc0) REG32((adc0) + 0x00000000U)
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#define ADC_CTL0(adc0) REG32((adc0) + 0x00000004U)
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#define ADC_CTL1(adc0) REG32((adc0) + 0x00000008U)
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#define ADC_SAMPT0(adc0) REG32((adc0) + 0x0000000CU)
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#define ADC_SAMPT1(adc0) REG32((adc0) + 0x00000010U)
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#define ADC_RSQ2(adc0) REG32((adc0) + 0x00000034U)
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#define ADC_RDATA(adc0) REG32((adc0) + 0x0000004CU)
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#endif
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#define SPT_WIDTH 3U
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#define SAMPT1_SIZE 10U
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#if defined(CONFIG_SOC_SERIES_GD32F4XX)
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#define SMP_TIME(x) ADC_SAMPLETIME_##x
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static const uint16_t acq_time_tbl[8] = {3, 15, 28, 56, 84, 112, 144, 480};
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static const uint32_t table_samp_time[] = {
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SMP_TIME(3),
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SMP_TIME(15),
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SMP_TIME(28),
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SMP_TIME(56),
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SMP_TIME(84),
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SMP_TIME(112),
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SMP_TIME(144),
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SMP_TIME(480)
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};
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#elif defined(CONFIG_SOC_SERIES_GD32L23X)
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#define SMP_TIME(x) ADC_SAMPLETIME_##x##POINT5
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static const uint16_t acq_time_tbl[8] = {3, 8, 14, 29, 42, 56, 72, 240};
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static const uint32_t table_samp_time[] = {
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SMP_TIME(2),
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SMP_TIME(7),
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SMP_TIME(13),
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SMP_TIME(28),
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SMP_TIME(41),
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SMP_TIME(55),
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SMP_TIME(71),
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SMP_TIME(239),
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};
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#elif defined(CONFIG_SOC_SERIES_GD32A50X)
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#define SMP_TIME(x) ADC_SAMPLETIME_##x##POINT5
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static const uint16_t acq_time_tbl[8] = {3, 15, 28, 56, 84, 112, 144, 480};
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static const uint32_t table_samp_time[] = {
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SMP_TIME(2),
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SMP_TIME(14),
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SMP_TIME(27),
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SMP_TIME(55),
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SMP_TIME(83),
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SMP_TIME(111),
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SMP_TIME(143),
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SMP_TIME(479)
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};
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#else
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#define SMP_TIME(x) ADC_SAMPLETIME_##x##POINT5
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static const uint16_t acq_time_tbl[8] = {2, 8, 14, 29, 42, 56, 72, 240};
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static const uint32_t table_samp_time[] = {
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SMP_TIME(1),
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SMP_TIME(7),
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SMP_TIME(13),
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SMP_TIME(28),
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SMP_TIME(41),
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SMP_TIME(55),
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SMP_TIME(71),
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SMP_TIME(239)
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};
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#endif
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struct adc_gd32_config {
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uint32_t reg;
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#ifdef CONFIG_SOC_SERIES_GD32F3X0
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uint32_t rcu_clock_source;
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#endif
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uint16_t clkid;
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struct reset_dt_spec reset;
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uint8_t channels;
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const struct pinctrl_dev_config *pcfg;
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uint8_t irq_num;
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void (*irq_config_func)(void);
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};
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struct adc_gd32_data {
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struct adc_context ctx;
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const struct device *dev;
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uint16_t *buffer;
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uint16_t *repeat_buffer;
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};
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static void adc_gd32_isr(const struct device *dev)
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{
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struct adc_gd32_data *data = dev->data;
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const struct adc_gd32_config *cfg = dev->config;
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if (ADC_STAT(cfg->reg) & ADC_STAT_EOC) {
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*data->buffer++ = ADC_RDATA(cfg->reg);
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/* Disable EOC interrupt. */
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ADC_CTL0(cfg->reg) &= ~ADC_CTL0_EOCIE;
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/* Clear EOC bit. */
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ADC_STAT(cfg->reg) &= ~ADC_STAT_EOC;
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adc_context_on_sampling_done(&data->ctx, dev);
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}
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}
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static void adc_context_start_sampling(struct adc_context *ctx)
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{
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struct adc_gd32_data *data = CONTAINER_OF(ctx, struct adc_gd32_data, ctx);
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const struct device *dev = data->dev;
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const struct adc_gd32_config *cfg = dev->config;
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data->repeat_buffer = data->buffer;
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/* Enable EOC interrupt */
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ADC_CTL0(cfg->reg) |= ADC_CTL0_EOCIE;
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/* Set ADC software conversion trigger. */
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ADC_CTL1(cfg->reg) |= ADC_CTL1_SWRCST;
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}
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static void adc_context_update_buffer_pointer(struct adc_context *ctx,
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bool repeat_sampling)
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{
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struct adc_gd32_data *data = CONTAINER_OF(ctx, struct adc_gd32_data, ctx);
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if (repeat_sampling) {
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data->buffer = data->repeat_buffer;
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}
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}
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static inline void adc_gd32_calibration(const struct adc_gd32_config *cfg)
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{
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ADC_CTL1(cfg->reg) |= ADC_CTL1_RSTCLB;
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/* Wait for calibration registers initialized. */
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while (ADC_CTL1(cfg->reg) & ADC_CTL1_RSTCLB) {
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}
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ADC_CTL1(cfg->reg) |= ADC_CTL1_CLB;
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/* Wait for calibration complete. */
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while (ADC_CTL1(cfg->reg) & ADC_CTL1_CLB) {
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}
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}
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static int adc_gd32_configure_sampt(const struct adc_gd32_config *cfg,
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uint8_t channel, uint16_t acq_time)
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{
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uint8_t index = 0, offset;
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if (acq_time != ADC_ACQ_TIME_DEFAULT) {
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/* Acquisition time unit is adc clock cycle. */
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if (ADC_ACQ_TIME_UNIT(acq_time) != ADC_ACQ_TIME_TICKS) {
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return -EINVAL;
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}
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for ( ; index < ARRAY_SIZE(acq_time_tbl); index++) {
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if (ADC_ACQ_TIME_VALUE(acq_time) <= acq_time_tbl[index]) {
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break;
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}
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}
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if (ADC_ACQ_TIME_VALUE(acq_time) != acq_time_tbl[index]) {
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return -ENOTSUP;
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}
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}
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if (channel < SAMPT1_SIZE) {
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offset = SPT_WIDTH * channel;
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ADC_SAMPT1(cfg->reg) &= ~(ADC_SAMPTX_SPTN << offset);
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ADC_SAMPT1(cfg->reg) |= table_samp_time[index] << offset;
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} else {
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offset = SPT_WIDTH * (channel - SAMPT1_SIZE);
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ADC_SAMPT0(cfg->reg) &= ~(ADC_SAMPTX_SPTN << offset);
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ADC_SAMPT0(cfg->reg) |= table_samp_time[index] << offset;
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}
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return 0;
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}
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static int adc_gd32_channel_setup(const struct device *dev,
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const struct adc_channel_cfg *chan_cfg)
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{
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const struct adc_gd32_config *cfg = dev->config;
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if (chan_cfg->gain != ADC_GAIN_1) {
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LOG_ERR("Gain is not valid");
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return -ENOTSUP;
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}
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if (chan_cfg->reference != ADC_REF_INTERNAL) {
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LOG_ERR("Reference is not valid");
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return -ENOTSUP;
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}
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if (chan_cfg->differential) {
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LOG_ERR("Differential sampling not supported");
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return -ENOTSUP;
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}
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if (chan_cfg->channel_id >= cfg->channels) {
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LOG_ERR("Invalid channel (%u)", chan_cfg->channel_id);
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return -EINVAL;
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}
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return adc_gd32_configure_sampt(cfg, chan_cfg->channel_id,
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chan_cfg->acquisition_time);
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}
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static int adc_gd32_start_read(const struct device *dev,
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const struct adc_sequence *sequence)
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{
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struct adc_gd32_data *data = dev->data;
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const struct adc_gd32_config *cfg = dev->config;
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uint8_t resolution_id;
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uint32_t index;
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index = find_lsb_set(sequence->channels) - 1;
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if (sequence->channels > BIT(index)) {
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LOG_ERR("Only single channel supported");
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return -ENOTSUP;
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}
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switch (sequence->resolution) {
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case 12U:
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resolution_id = 0U;
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break;
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case 10U:
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resolution_id = 1U;
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break;
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case 8U:
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resolution_id = 2U;
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break;
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case 6U:
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resolution_id = 3U;
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break;
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default:
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return -EINVAL;
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}
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#if defined(CONFIG_SOC_SERIES_GD32F4XX) || \
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defined(CONFIG_SOC_SERIES_GD32F3X0) || \
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defined(CONFIG_SOC_SERIES_GD32L23X)
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ADC_CTL0(cfg->reg) &= ~ADC_CTL0_DRES;
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ADC_CTL0(cfg->reg) |= CTL0_DRES(resolution_id);
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#elif defined(CONFIG_SOC_SERIES_GD32F403) || \
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defined(CONFIG_SOC_SERIES_GD32A50X)
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ADC_OVSAMPCTL(cfg->reg) &= ~ADC_OVSAMPCTL_DRES;
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ADC_OVSAMPCTL(cfg->reg) |= OVSAMPCTL_DRES(resolution_id);
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#elif defined(CONFIG_SOC_SERIES_GD32VF103)
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ADC_OVSCR(cfg->reg) &= ~ADC_OVSCR_DRES;
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ADC_OVSCR(cfg->reg) |= OVSCR_DRES(resolution_id);
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#endif
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if (sequence->calibrate) {
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adc_gd32_calibration(cfg);
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}
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/* Signle conversion mode with regular group. */
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ADC_RSQ2(cfg->reg) &= ~ADC_RSQX_RSQN;
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ADC_RSQ2(cfg->reg) = index;
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data->buffer = sequence->buffer;
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adc_context_start_read(&data->ctx, sequence);
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return adc_context_wait_for_completion(&data->ctx);
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}
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static int adc_gd32_read(const struct device *dev,
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const struct adc_sequence *sequence)
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{
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struct adc_gd32_data *data = dev->data;
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int error;
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adc_context_lock(&data->ctx, false, NULL);
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error = adc_gd32_start_read(dev, sequence);
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adc_context_release(&data->ctx, error);
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return error;
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}
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#ifdef CONFIG_ADC_ASYNC
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static int adc_gd32_read_async(const struct device *dev,
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const struct adc_sequence *sequence,
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struct k_poll_signal *async)
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{
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struct adc_gd32_data *data = dev->data;
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int error;
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adc_context_lock(&data->ctx, true, async);
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error = adc_gd32_start_read(dev, sequence);
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adc_context_release(&data->ctx, error);
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return error;
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}
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#endif /* CONFIG_ADC_ASYNC */
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static struct adc_driver_api adc_gd32_driver_api = {
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.channel_setup = adc_gd32_channel_setup,
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.read = adc_gd32_read,
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#ifdef CONFIG_ADC_ASYNC
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.read_async = adc_gd32_read_async,
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#endif /* CONFIG_ADC_ASYNC */
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};
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static int adc_gd32_init(const struct device *dev)
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{
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struct adc_gd32_data *data = dev->data;
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const struct adc_gd32_config *cfg = dev->config;
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int ret;
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data->dev = dev;
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ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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return ret;
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}
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#ifdef CONFIG_SOC_SERIES_GD32F3X0
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/* Select adc clock source and its prescaler. */
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rcu_adc_clock_config(cfg->rcu_clock_source);
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#endif
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(void)clock_control_on(GD32_CLOCK_CONTROLLER,
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(clock_control_subsys_t)&cfg->clkid);
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(void)reset_line_toggle_dt(&cfg->reset);
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#if defined(CONFIG_SOC_SERIES_GD32F403) || \
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defined(CONFIG_SOC_SERIES_GD32VF103) || \
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defined(CONFIG_SOC_SERIES_GD32F3X0) || \
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defined(CONFIG_SOC_SERIES_GD32L23X)
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/* Set SWRCST as the regular channel external trigger. */
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ADC_CTL1(cfg->reg) &= ~ADC_CTL1_ETSRC;
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ADC_CTL1(cfg->reg) |= CTL1_ETSRC(7);
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/* Enable external trigger for regular channel. */
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ADC_CTL1(cfg->reg) |= ADC_CTL1_ETERC;
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#endif
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#ifdef CONFIG_SOC_SERIES_GD32A50X
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ADC_CTL1(cfg->reg) |= ADC_CTL1_ETSRC;
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ADC_CTL1(cfg->reg) |= ADC_CTL1_ETERC;
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#endif
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/* Enable ADC */
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ADC_CTL1(cfg->reg) |= ADC_CTL1_ADCON;
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adc_gd32_calibration(cfg);
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cfg->irq_config_func();
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adc_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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#define HANDLE_SHARED_IRQ(n, active_irq) \
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static const struct device *const dev_##n = DEVICE_DT_INST_GET(n); \
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const struct adc_gd32_config *cfg_##n = dev_##n->config; \
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\
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if ((cfg_##n->irq_num == active_irq) && \
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(ADC_CTL0(cfg_##n->reg) & ADC_CTL0_EOCIE)) { \
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adc_gd32_isr(dev_##n); \
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}
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static void adc_gd32_global_irq_handler(const struct device *dev)
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{
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const struct adc_gd32_config *cfg = dev->config;
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LOG_DBG("global irq handler: %u", cfg->irq_num);
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DT_INST_FOREACH_STATUS_OKAY_VARGS(HANDLE_SHARED_IRQ, (cfg->irq_num));
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}
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static void adc_gd32_global_irq_cfg(void)
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{
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static bool global_irq_init = true;
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if (!global_irq_init) {
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return;
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}
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global_irq_init = false;
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#if ADC0_ENABLE
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/* Shared irq config default to adc0. */
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IRQ_CONNECT(DT_IRQN(ADC0_NODE),
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DT_IRQ(ADC0_NODE, priority),
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adc_gd32_global_irq_handler,
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DEVICE_DT_GET(ADC0_NODE),
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0);
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irq_enable(DT_IRQN(ADC0_NODE));
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#elif ADC1_ENABLE
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IRQ_CONNECT(DT_IRQN(ADC1_NODE),
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DT_IRQ(ADC1_NODE, priority),
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adc_gd32_global_irq_handler,
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DEVICE_DT_GET(ADC1_NODE),
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0);
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irq_enable(DT_IRQN(ADC1_NODE));
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#endif
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#if (ADC0_ENABLE || ADC1_ENABLE) && \
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defined(CONFIG_SOC_SERIES_GD32F4XX)
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/* gd32f4xx adc2 share the same irq number with adc0 and adc1. */
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#elif ADC2_ENABLE
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IRQ_CONNECT(DT_IRQN(ADC2_NODE),
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DT_IRQ(ADC2_NODE, priority),
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adc_gd32_global_irq_handler,
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DEVICE_DT_GET(ADC2_NODE),
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0);
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irq_enable(DT_IRQN(ADC2_NODE));
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#endif
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}
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#ifdef CONFIG_SOC_SERIES_GD32F3X0
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#define ADC_CLOCK_SOURCE(n) \
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.rcu_clock_source = DT_INST_PROP(n, rcu_clock_source)
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#else
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#define ADC_CLOCK_SOURCE(n)
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#endif
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#define ADC_GD32_INIT(n) \
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PINCTRL_DT_INST_DEFINE(n); \
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static struct adc_gd32_data adc_gd32_data_##n = { \
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ADC_CONTEXT_INIT_TIMER(adc_gd32_data_##n, ctx), \
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ADC_CONTEXT_INIT_LOCK(adc_gd32_data_##n, ctx), \
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ADC_CONTEXT_INIT_SYNC(adc_gd32_data_##n, ctx), \
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}; \
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const static struct adc_gd32_config adc_gd32_config_##n = { \
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.reg = DT_INST_REG_ADDR(n), \
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.clkid = DT_INST_CLOCKS_CELL(n, id), \
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.reset = RESET_DT_SPEC_INST_GET(n), \
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.channels = DT_INST_PROP(n, channels), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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.irq_num = DT_INST_IRQN(n), \
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.irq_config_func = adc_gd32_global_irq_cfg, \
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ADC_CLOCK_SOURCE(n) \
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}; \
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DEVICE_DT_INST_DEFINE(n, \
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&adc_gd32_init, NULL, \
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&adc_gd32_data_##n, &adc_gd32_config_##n, \
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POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, \
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&adc_gd32_driver_api); \
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|
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DT_INST_FOREACH_STATUS_OKAY(ADC_GD32_INIT)
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