440 lines
14 KiB
C
440 lines
14 KiB
C
/*
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* Copyright (c) 2024 Ambiq Micro Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ambiq_adc
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#include <zephyr/drivers/adc.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/pm/device.h>
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#include <zephyr/pm/device_runtime.h>
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#include <zephyr/kernel.h>
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#define ADC_CONTEXT_USES_KERNEL_TIMER
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#include "adc_context.h"
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/* ambiq-sdk includes */
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#include <am_mcu_apollo.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(adc_ambiq, CONFIG_ADC_LOG_LEVEL);
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typedef int (*ambiq_adc_pwr_func_t)(void);
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#define PWRCTRL_MAX_WAIT_US 5
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/* Number of slots available. */
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#define AMBIQ_ADC_SLOT_NUMBER AM_HAL_ADC_MAX_SLOTS
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struct adc_ambiq_config {
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uint32_t base;
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int size;
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uint8_t num_channels;
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void (*irq_config_func)(void);
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const struct pinctrl_dev_config *pin_cfg;
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ambiq_adc_pwr_func_t pwr_func;
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};
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struct adc_ambiq_data {
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struct adc_context ctx;
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void *adcHandle;
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uint16_t *buffer;
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uint16_t *repeat_buffer;
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uint8_t active_channels;
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};
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static int adc_ambiq_set_resolution(am_hal_adc_slot_prec_e *prec, uint8_t adc_resolution)
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{
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switch (adc_resolution) {
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case 8:
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*prec = AM_HAL_ADC_SLOT_8BIT;
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break;
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case 10:
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*prec = AM_HAL_ADC_SLOT_10BIT;
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break;
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case 12:
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*prec = AM_HAL_ADC_SLOT_12BIT;
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break;
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#if !defined(CONFIG_SOC_SERIES_APOLLO4X)
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case 14:
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*prec = AM_HAL_ADC_SLOT_14BIT;
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break;
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#endif
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static int adc_ambiq_slot_config(const struct device *dev, const struct adc_sequence *sequence,
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am_hal_adc_slot_chan_e channel, uint32_t ui32SlotNumber)
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{
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struct adc_ambiq_data *data = dev->data;
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am_hal_adc_slot_config_t ADCSlotConfig;
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if (adc_ambiq_set_resolution(&ADCSlotConfig.ePrecisionMode, sequence->resolution) != 0) {
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LOG_ERR("unsupported resolution %d", sequence->resolution);
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return -ENOTSUP;
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}
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/* Set up an ADC slot */
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ADCSlotConfig.eMeasToAvg = AM_HAL_ADC_SLOT_AVG_1;
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ADCSlotConfig.eChannel = channel;
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ADCSlotConfig.bWindowCompare = false;
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ADCSlotConfig.bEnabled = true;
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#if defined(CONFIG_SOC_SERIES_APOLLO4X)
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ADCSlotConfig.ui32TrkCyc = AM_HAL_ADC_MIN_TRKCYC;
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#endif
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if (AM_HAL_STATUS_SUCCESS !=
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am_hal_adc_configure_slot(data->adcHandle, ui32SlotNumber, &ADCSlotConfig)) {
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LOG_ERR("configuring ADC Slot 0 failed.\n");
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return -ENODEV;
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}
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return 0;
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}
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static void adc_ambiq_isr(const struct device *dev)
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{
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struct adc_ambiq_data *data = dev->data;
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uint32_t ui32IntMask;
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uint32_t ui32NumSamples;
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am_hal_adc_sample_t Sample;
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/* Read the interrupt status. */
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am_hal_adc_interrupt_status(data->adcHandle, &ui32IntMask, true);
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/* Clear the ADC interrupt.*/
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am_hal_adc_interrupt_clear(data->adcHandle, ui32IntMask);
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/*
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* If we got a conversion completion interrupt (which should be our only
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* ADC interrupt), go ahead and read the data.
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*/
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if (ui32IntMask & AM_HAL_ADC_INT_CNVCMP) {
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for (uint32_t i = 0; i < data->active_channels; i++) {
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/* Read the value from the FIFO. */
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ui32NumSamples = 1;
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am_hal_adc_samples_read(data->adcHandle, false, NULL, &ui32NumSamples,
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&Sample);
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*data->buffer++ = Sample.ui32Sample;
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}
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adc_context_on_sampling_done(&data->ctx, dev);
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}
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}
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static int adc_ambiq_check_buffer_size(const struct adc_sequence *sequence, uint8_t active_channels)
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{
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size_t needed_buffer_size;
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needed_buffer_size = active_channels * sizeof(uint16_t);
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if (sequence->options) {
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needed_buffer_size *= (1 + sequence->options->extra_samplings);
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}
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if (sequence->buffer_size < needed_buffer_size) {
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LOG_DBG("Provided buffer is too small (%u/%u)", sequence->buffer_size,
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needed_buffer_size);
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return -ENOMEM;
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}
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return 0;
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}
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static int adc_ambiq_start_read(const struct device *dev, const struct adc_sequence *sequence)
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{
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struct adc_ambiq_data *data = dev->data;
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const struct adc_ambiq_config *cfg = dev->config;
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uint8_t channel_id = 0;
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uint32_t channels = 0;
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uint8_t active_channels = 0;
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uint8_t slot_index;
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int error = 0;
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if (sequence->channels & ~BIT_MASK(cfg->num_channels)) {
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LOG_ERR("Incorrect channels, bitmask 0x%x", sequence->channels);
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return -EINVAL;
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}
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if (sequence->channels == 0UL) {
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LOG_ERR("No channel selected");
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return -EINVAL;
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}
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error = adc_ambiq_check_buffer_size(sequence, active_channels);
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if (error < 0) {
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return error;
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}
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active_channels = POPCOUNT(sequence->channels);
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if (active_channels > AMBIQ_ADC_SLOT_NUMBER) {
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LOG_ERR("Too many channels for sequencer. Max: %d", AMBIQ_ADC_SLOT_NUMBER);
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return -ENOTSUP;
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}
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channels = sequence->channels;
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for (slot_index = 0; slot_index < active_channels; slot_index++) {
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channel_id = find_lsb_set(channels) - 1;
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error = adc_ambiq_slot_config(dev, sequence, channel_id, slot_index);
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if (error < 0) {
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return error;
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}
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channels &= ~BIT(channel_id);
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}
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__ASSERT_NO_MSG(channels == 0);
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/* Enable the ADC. */
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am_hal_adc_enable(data->adcHandle);
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data->active_channels = active_channels;
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data->buffer = sequence->buffer;
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/* Start ADC conversion */
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adc_context_start_read(&data->ctx, sequence);
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error = adc_context_wait_for_completion(&data->ctx);
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return error;
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}
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static int adc_ambiq_read(const struct device *dev, const struct adc_sequence *sequence)
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{
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struct adc_ambiq_data *data = dev->data;
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int error = 0;
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error = pm_device_runtime_get(dev);
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if (error < 0) {
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LOG_ERR("pm_device_runtime_get failed: %d", error);
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}
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adc_context_lock(&data->ctx, false, NULL);
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error = adc_ambiq_start_read(dev, sequence);
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adc_context_release(&data->ctx, error);
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int ret = error;
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error = pm_device_runtime_put(dev);
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if (error < 0) {
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LOG_ERR("pm_device_runtime_put failed: %d", error);
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}
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error = ret;
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return error;
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}
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static int adc_ambiq_channel_setup(const struct device *dev, const struct adc_channel_cfg *chan_cfg)
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{
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const struct adc_ambiq_config *cfg = dev->config;
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if (chan_cfg->channel_id >= cfg->num_channels) {
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LOG_ERR("unsupported channel id '%d'", chan_cfg->channel_id);
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return -ENOTSUP;
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}
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if (chan_cfg->gain != ADC_GAIN_1) {
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LOG_ERR("Gain is not valid");
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return -ENOTSUP;
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}
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if (chan_cfg->reference != ADC_REF_INTERNAL) {
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LOG_ERR("Reference is not valid");
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return -ENOTSUP;
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}
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if (chan_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
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LOG_ERR("unsupported acquisition_time '%d'", chan_cfg->acquisition_time);
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return -ENOTSUP;
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}
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if (chan_cfg->differential) {
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LOG_ERR("Differential sampling not supported");
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return -ENOTSUP;
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}
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return 0;
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}
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static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
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{
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struct adc_ambiq_data *data = CONTAINER_OF(ctx, struct adc_ambiq_data, ctx);
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if (repeat_sampling) {
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data->buffer = data->repeat_buffer;
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}
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}
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static void adc_context_start_sampling(struct adc_context *ctx)
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{
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struct adc_ambiq_data *data = CONTAINER_OF(ctx, struct adc_ambiq_data, ctx);
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data->repeat_buffer = data->buffer;
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/*Trigger the ADC*/
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am_hal_adc_sw_trigger(data->adcHandle);
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}
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static int adc_ambiq_init(const struct device *dev)
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{
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struct adc_ambiq_data *data = dev->data;
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const struct adc_ambiq_config *cfg = dev->config;
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am_hal_adc_config_t ADCConfig;
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int ret;
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/* Initialize the ADC and get the handle*/
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if (AM_HAL_STATUS_SUCCESS !=
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am_hal_adc_initialize((cfg->base - ADC_BASE) / (cfg->size * 4), &data->adcHandle)) {
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ret = -ENODEV;
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LOG_ERR("Faile to initialize ADC, code:%d", ret);
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return ret;
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}
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/* power on ADC*/
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ret = cfg->pwr_func();
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/* Set up the ADC configuration parameters. These settings are reasonable
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* for accurate measurements at a low sample rate.
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*/
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#if !defined(CONFIG_SOC_SERIES_APOLLO4X)
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ADCConfig.eClock = AM_HAL_ADC_CLKSEL_HFRC;
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ADCConfig.eReference = AM_HAL_ADC_REFSEL_INT_1P5;
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#else
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ADCConfig.eClock = AM_HAL_ADC_CLKSEL_HFRC_24MHZ;
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ADCConfig.eRepeatTrigger = AM_HAL_ADC_RPTTRIGSEL_TMR,
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#endif
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ADCConfig.ePolarity = AM_HAL_ADC_TRIGPOL_RISING;
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ADCConfig.eTrigger = AM_HAL_ADC_TRIGSEL_SOFTWARE;
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ADCConfig.eClockMode = AM_HAL_ADC_CLKMODE_LOW_POWER;
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ADCConfig.ePowerMode = AM_HAL_ADC_LPMODE0;
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ADCConfig.eRepeat = AM_HAL_ADC_SINGLE_SCAN;
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if (AM_HAL_STATUS_SUCCESS != am_hal_adc_configure(data->adcHandle, &ADCConfig)) {
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ret = -ENODEV;
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LOG_ERR("Configuring ADC failed, code:%d", ret);
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return ret;
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}
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ret = pinctrl_apply_state(cfg->pin_cfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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return ret;
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}
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/* Enable the ADC interrupts in the ADC. */
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cfg->irq_config_func();
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am_hal_adc_interrupt_enable(data->adcHandle, AM_HAL_ADC_INT_CNVCMP);
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adc_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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#ifdef CONFIG_ADC_ASYNC
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static int adc_ambiq_read_async(const struct device *dev, const struct adc_sequence *sequence,
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struct k_poll_signal *async)
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{
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struct adc_ambiq_data *data = dev->data;
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int error = 0;
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error = pm_device_runtime_get(dev);
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if (error < 0) {
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LOG_ERR("pm_device_runtime_get failed: %d", error);
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}
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adc_context_lock(&data->ctx, true, async);
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error = adc_ambiq_start_read(dev, sequence);
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adc_context_release(&data->ctx, error);
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int ret = error;
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error = pm_device_runtime_put(dev);
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if (error < 0) {
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LOG_ERR("pm_device_runtime_put failed: %d", error);
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}
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error = ret;
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return error;
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}
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#endif
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#ifdef CONFIG_PM_DEVICE
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static int adc_ambiq_pm_action(const struct device *dev, enum pm_device_action action)
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{
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struct adc_ambiq_data *data = dev->data;
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uint32_t ret = 0;
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am_hal_sysctrl_power_state_e status;
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switch (action) {
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case PM_DEVICE_ACTION_RESUME:
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status = AM_HAL_SYSCTRL_WAKE;
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break;
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case PM_DEVICE_ACTION_SUSPEND:
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status = AM_HAL_SYSCTRL_DEEPSLEEP;
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break;
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default:
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return -ENOTSUP;
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}
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ret = am_hal_adc_power_control(data->adcHandle, status, true);
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if (ret != AM_HAL_STATUS_SUCCESS) {
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return -EPERM;
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} else {
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return 0;
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}
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}
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#endif /* CONFIG_PM_DEVICE */
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#ifdef CONFIG_ADC_ASYNC
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#define ADC_AMBIQ_DRIVER_API(n) \
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static const struct adc_driver_api adc_ambiq_driver_api_##n = { \
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.channel_setup = adc_ambiq_channel_setup, \
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.read = adc_ambiq_read, \
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.read_async = adc_ambiq_read_async, \
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.ref_internal = DT_INST_PROP(n, internal_vref_mv), \
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};
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#else
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#define ADC_AMBIQ_DRIVER_API(n) \
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static const struct adc_driver_api adc_ambiq_driver_api_##n = { \
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.channel_setup = adc_ambiq_channel_setup, \
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.read = adc_ambiq_read, \
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.ref_internal = DT_INST_PROP(n, internal_vref_mv), \
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};
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#endif
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#define ADC_AMBIQ_INIT(n) \
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PINCTRL_DT_INST_DEFINE(n); \
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ADC_AMBIQ_DRIVER_API(n); \
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static int pwr_on_ambiq_adc_##n(void) \
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{ \
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uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) + \
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DT_INST_PHA(n, ambiq_pwrcfg, offset); \
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sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
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k_busy_wait(PWRCTRL_MAX_WAIT_US); \
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return 0; \
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} \
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static void adc_irq_config_func_##n(void) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), adc_ambiq_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQN(n)); \
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}; \
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static struct adc_ambiq_data adc_ambiq_data_##n = { \
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ADC_CONTEXT_INIT_TIMER(adc_ambiq_data_##n, ctx), \
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ADC_CONTEXT_INIT_LOCK(adc_ambiq_data_##n, ctx), \
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ADC_CONTEXT_INIT_SYNC(adc_ambiq_data_##n, ctx), \
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}; \
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const static struct adc_ambiq_config adc_ambiq_config_##n = { \
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.base = DT_INST_REG_ADDR(n), \
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.size = DT_INST_REG_SIZE(n), \
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.num_channels = DT_PROP(DT_DRV_INST(n), channel_count), \
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.irq_config_func = adc_irq_config_func_##n, \
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.pin_cfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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.pwr_func = pwr_on_ambiq_adc_##n, \
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}; \
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PM_DEVICE_DT_INST_DEFINE(n, adc_ambiq_pm_action); \
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DEVICE_DT_INST_DEFINE(n, &adc_ambiq_init, PM_DEVICE_DT_INST_GET(n), &adc_ambiq_data_##n, \
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&adc_ambiq_config_##n, POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, \
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&adc_ambiq_driver_api_##n);
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DT_INST_FOREACH_STATUS_OKAY(ADC_AMBIQ_INIT)
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