zephyr/arch/xtensa/core
Guennadi Liakhovetski d676d469bd LLEXT: Xtensa: add support for L32R relocation
When building LLEXT for Xtensa with custom sections the compiler
can leave unresolved references in them. Then this has to be done by
the LLEXT core during linking. This commit adds linking support for
the L32R Xtensa instruction.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2024-09-29 21:21:24 +02:00
..
offsets
startup
CMakeLists.txt
README_MMU.txt
README_WINDOWS.rst
coredump.c xtensa: coredump: support dumping privilege stack 2024-09-21 11:29:39 +02:00
cpu_idle.c
crt1.S
debug_helpers_asm.S
elf.c LLEXT: Xtensa: add support for L32R relocation 2024-09-29 21:21:24 +02:00
fatal.c
gdbstub.c
gen_vectors.py
gen_zsr.py
irq_manage.c
irq_offload.c arch: initialize irq_offload during boot, do not use SYS_INIT 2024-09-17 20:05:22 -04:00
mem_manage.c
mmu.c
mpu.c
prep_c.c cache: add new interface arch_cache_init() for initializing cache 2024-09-17 20:05:22 -04:00
ptables.c
smp.c
syscall_helper.c
thread.c arch: kernel: lib: toolchain: Standardize TLS keyword 2024-09-23 10:01:48 +02:00
timing.c
tls.c
userspace.S
vector_handlers.c
window_vectors.S
xcc_stubs.c
xtensa_asm2_util.S
xtensa_backtrace.c
xtensa_hifi.S
xtensa_intgen.py
xtensa_intgen.tmpl