124 lines
3.1 KiB
C
124 lines
3.1 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <device.h>
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#include <i2c.h>
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#include <init.h>
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#include "qm_i2c.h"
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#include "qm_scss.h"
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static int i2c_qmsi_configure(struct device *dev, uint32_t config)
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{
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union dev_config cfg;
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qm_i2c_config_t qm_cfg;
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cfg.raw = config;
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/* This driver only supports master mode. */
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if (!cfg.bits.is_master_device)
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return DEV_INVALID_CONF;
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qm_cfg.mode = QM_I2C_MASTER;
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qm_cfg.address_mode = (cfg.bits.use_10_bit_addr) ? QM_I2C_10_BIT :
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QM_I2C_7_BIT;
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switch (cfg.bits.speed) {
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case I2C_SPEED_STANDARD:
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qm_cfg.speed = QM_I2C_SPEED_STD;
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break;
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case I2C_SPEED_FAST:
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qm_cfg.speed = QM_I2C_SPEED_FAST;
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break;
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case QM_I2C_SPEED_FAST_PLUS:
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qm_cfg.speed = QM_I2C_SPEED_FAST_PLUS;
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break;
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default:
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return DEV_INVALID_CONF;
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}
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if (qm_i2c_set_config(QM_I2C_0, &qm_cfg) != QM_RC_OK) {
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clk_periph_disable(CLK_PERIPH_I2C_M0_REGISTER);
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return DEV_FAIL;
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}
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return DEV_OK;
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}
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/* FIXME: This function is implemented using QMSI polling APIs since
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* the interrupt API (qm_i2c_master_irq_transfer) seems not to be
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* working properly. Once this issue is solved, we should change this
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* function to use the interrupt API and sleep the current thread while
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* the I2C transfer is carried out.
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*/
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static int i2c_qmsi_transfer(struct device *dev, struct i2c_msg *msgs,
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uint8_t num_msgs, uint16_t addr)
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{
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qm_rc_t rc;
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if (qm_i2c_get_status(QM_I2C_0) != QM_I2C_IDLE)
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return DEV_USED;
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if (msgs == NULL || num_msgs == 0)
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return DEV_INVALID_OP;
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for (int i = 0; i < num_msgs; i++) {
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uint8_t *buf = msgs[i].buf;
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uint32_t len = msgs[i].len;
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uint8_t op = msgs[i].flags & I2C_MSG_RW_MASK;
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bool stop = (msgs[i].flags & I2C_MSG_STOP) == I2C_MSG_STOP;
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rc = (op == I2C_MSG_WRITE) ?
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qm_i2c_master_write(QM_I2C_0, addr, buf, len, stop) :
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qm_i2c_master_read(QM_I2C_0, addr, buf, len, stop);
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if (rc != QM_RC_OK)
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return DEV_FAIL;
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}
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return DEV_OK;
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}
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static int i2c_qmsi_suspend(struct device *dev)
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{
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return DEV_NO_SUPPORT;
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}
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static int i2c_qmsi_resume(struct device *dev)
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{
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return DEV_NO_SUPPORT;
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}
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static struct i2c_driver_api api = {
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.configure = i2c_qmsi_configure,
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.transfer = i2c_qmsi_transfer,
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.suspend = i2c_qmsi_suspend,
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.resume = i2c_qmsi_resume,
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};
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static int i2c_qmsi_init(struct device *dev)
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{
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clk_periph_enable(CLK_PERIPH_I2C_M0_REGISTER);
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dev->driver_api = &api;
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return 0;
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}
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DECLARE_DEVICE_INIT_CONFIG(i2c_qmsi_0, CONFIG_I2C_QMSI_0_NAME, i2c_qmsi_init,
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NULL);
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SYS_DEFINE_DEVICE(i2c_qmsi_0, 0, SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
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