211 lines
6.7 KiB
C
211 lines
6.7 KiB
C
/**
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* Synopsys DesignWare Sensor and Control IP Subsystem IO Software Driver and
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* documentation (hereinafter, "Software") is an Unsupported proprietary work
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* of Synopsys, Inc. unless otherwise expressly agreed to in writing between
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* Synopsys and you.
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*
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* The Software IS NOT an item of Licensed Software or Licensed Product under
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* any End User Software License Agreement or Agreement for Licensed Product
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* with Synopsys or any supplement thereto. You are permitted to use and
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* redistribute this Software in source and binary forms, with or without
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* modification, provided that redistributions of source code must retain this
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* notice. You may not view, use, disclose, copy or distribute this file or
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* any information contained herein except pursuant to this license grant from
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* Synopsys. If you do not agree with this notice, including the disclaimer
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* below, then you are not authorized to use the Software.
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*
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* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGE.
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*/
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/**
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* @file
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*
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* @brief Designware ADC header file
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*/
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#ifndef DW_ADC_H_
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#define DW_ADC_H_
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#include <stdint.h>
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#include <adc.h>
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/**
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* ADC driver name.
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*
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* Name for the singleton instance of the ADC driver.
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*
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*/
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#define ADC_DRV_NAME "adc"
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/**
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* Number of buffers.
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*
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* Number of reception buffers to be supported by the driver.
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*/
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#define BUFS_NUM 32
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/* EAI ADC device registers */
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#define ADC_SET (0x00)
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#define ADC_DIVSEQSTAT (0x01)
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#define ADC_SEQ (0x02)
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#define ADC_CTRL (0x03)
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#define ADC_INTSTAT (0x04)
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#define ADC_SAMPLE (0x05)
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/* Additional device registers */
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#define MST_CTL (0x00)
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#define SLV_OBSR (0x00)
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/* Sensor Subsystem Interrupt Routing Mask */
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#define INT_SS_ADC_ERR_MASK (0x400)
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#define INT_SS_ADC_IRQ_MASK (0x404)
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/* ADC Specific macros */
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#define ADC_POP_SAMPLE (0x80000000)
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#define ADC_FLUSH_RX (0x40000000)
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#define ADC_FTL_SET_MASK (0x00ffffff)
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#define ADC_SEQ_SIZE_SET_MASK (0x3fc0ffff)
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#define ADC_SEQ_MODE_SET_MASK (0x3fffdfff)
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#define ADC_CONFIG_SET_MASK (0x3fffe000)
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#define ADC_CLK_RATIO_MASK (0x1fffff)
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#define ADC_CLR_UNDRFLOW (1 << 18)
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#define ADC_CLR_OVERFLOW (1 << 17)
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#define ADC_CLR_DATA_A (1 << 16)
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#define ADC_SEQ_TABLE_RST (0x0040)
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#define ADC_SEQ_PTR_RST (0x0020)
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#define ADC_SEQ_START (0x0010)
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#define ADC_SEQ_STOP_MASK (0x078ec)
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#define ADC_INT_ENA_MASK (0x001e)
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#define ADC_INT_DSB (0x0F00)
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#define ADC_INT_ENABLE (0x0000)
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#define ADC_CLK_ENABLE (0x0004)
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#define ADC_ENABLE (0x0002)
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#define ADC_DISABLE (0x0)
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#define ADC_RESET (0x1)
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#define ADC_INT_DATA_A (0x1)
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#define ADC_INT_ERR (0x6)
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#define ADC_STATE_CLOSED 0
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#define ADC_STATE_DISABLED 1
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#define ADC_STATE_IDLE 2
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#define ADC_STATE_SAMPLING 3
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#define ADC_STATE_ERROR 4
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/* ADC control commands */
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#define IO_ADC0_FS (32)
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#define IO_ADC0_SE (32)
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#define IO_ADC_SET_CLK_DIVIDER (0x20)
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#define IO_ADC_SET_CONFIG (0x21)
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#define IO_ADC_SET_SEQ_TABLE (0x22)
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#define IO_ADC_SET_SEQ_MODE (0x23)
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#define IO_ADC_SET_SEQ_STOP (0x24)
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#define IO_ADC_SET_RX_THRESHOLD (0x25)
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#define IO_ADC_INPUT_SINGLE_END 0
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#define IO_ADC_INPUT_DIFF 1
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#define IO_ADC_OUTPUT_PARAL 0
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#define IO_ADC_OUTPUT_SERIAL 1
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#define IO_ADC_CAPTURE_RISING_EDGE 0
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#define IO_ADC_CAPTURE_FALLING_EDGE 1
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#define IO_ADC_SEQ_MODE_SINGLESHOT 0
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#define IO_ADC_SEQ_MODE_REPETITIVE 1
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#define ENABLE_SSS_INTERRUPTS ~(0x01 << 8)
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#define ENABLE_ADC (ADC_INT_ENABLE | ADC_CLK_ENABLE | ADC_SEQ_TABLE_RST)
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#define START_ADC_SEQ (ADC_SEQ_START | ADC_ENABLE | ADC_CLK_ENABLE)
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#define RESUME_ADC_CAPTURE (ADC_INT_DSB|ADC_CLK_ENABLE|ADC_SEQ_PTR_RST)
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#define FLUSH_ADC_ERRORS (ADC_INT_DSB|ADC_CLK_ENABLE|ADC_CLR_OVERFLOW|ADC_CLR_UNDRFLOW)
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/** mV = 3.3V*/
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#define ADC_VREF 3300
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/**
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*
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* @brief Converts ADC raw data into mV
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*
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* The ADC raw data readings are converted into mV:
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* result = (data * ADC_VREF) / (2^resolution).
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*
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* @param _data_ Raw data to be converted.
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* @param _resolution_ Resolution used during the data sampling.
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*
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* @return data read in mVolts.
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*/
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#define ss_adc_data_to_mv(_data_, _resolution_) \
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((_data_ * ADC_VREF) / (1 << _resolution_))
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typedef void (*adc_dw_config_t)(void);
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/** @brief ADC configuration
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* This structure defines the ADC configuration values
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* that define the ADC hardware instance and configuration.
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*/
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struct adc_config {
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/**Register base address for hardware registers.*/
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uint32_t reg_base;
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/**IIO address for the IRQ mask register.*/
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uint32_t reg_irq_mask;
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/**IIO address for the error mask register.*/
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uint32_t reg_err_mask;
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/**Input mode*/
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uint8_t in_mode;
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/**Output mode*/
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uint8_t out_mode;
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/**Capture mode*/
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uint8_t capture_mode;
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/**Sequence mode*/
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uint8_t seq_mode;
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/**Serial delay*/
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uint8_t serial_dly;
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/**Sample width*/
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uint8_t sample_width;
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/**Clock ratio*/
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uint32_t clock_ratio;
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/**Config handler*/
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adc_dw_config_t config_func;
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};
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/**@brief ADC information and data.
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*
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* This structure defines the data that will be used
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* during driver execution.
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*/
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struct adc_info {
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device_sync_call_t sync;
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/**State of execution of the driver*/
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uint8_t state;
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/**Current reception buffer index*/
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uint8_t index[BUFS_NUM];
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/**Sequence entries' array*/
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struct adc_seq_entry *entries;
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/**Sequence size*/
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uint8_t seq_size;
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};
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/**
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*
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* @brief ADC Initialization function.
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*
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* Inits device model for the ADC IP from Dataware.
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*
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* @param dev Pointer to the device structure descriptor that
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* will be initialized.
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*
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* @return Integer: 0 for success, error otherwise.
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*/
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int adc_dw_init(struct device *dev);
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#endif /* DW_ADC_H_ */
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