433 lines
12 KiB
C
433 lines
12 KiB
C
/*
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* Copyright (c) 2019 Linaro Limited
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* Copyright (c) 2020 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define LOG_DOMAIN flash_stm32wb
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#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(LOG_DOMAIN);
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#include <kernel.h>
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#include <device.h>
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#include <string.h>
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#include <drivers/flash.h>
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#include <init.h>
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#include <soc.h>
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#include <sys/__assert.h>
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#include "flash_stm32.h"
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#include "stm32_hsem.h"
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#if defined(CONFIG_BT)
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#include "shci.h"
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#endif
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#define STM32WBX_PAGE_SHIFT 12
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/* offset and len must be aligned on 8 for write,
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* positive and not beyond end of flash
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*/
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bool flash_stm32_valid_range(const struct device *dev, off_t offset,
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uint32_t len,
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bool write)
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{
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return (!write || (offset % 8 == 0 && len % 8 == 0U)) &&
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flash_stm32_range_exists(dev, offset, len);
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}
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/*
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* Up to 255 4K pages
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*/
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static uint32_t get_page(off_t offset)
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{
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return offset >> STM32WBX_PAGE_SHIFT;
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}
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static inline void flush_cache(FLASH_TypeDef *regs)
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{
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if (regs->ACR & FLASH_ACR_DCEN) {
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regs->ACR &= ~FLASH_ACR_DCEN;
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/* Datasheet: DCRST: Data cache reset
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* This bit can be written only when thes data cache is disabled
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*/
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regs->ACR |= FLASH_ACR_DCRST;
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regs->ACR &= ~FLASH_ACR_DCRST;
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regs->ACR |= FLASH_ACR_DCEN;
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}
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if (regs->ACR & FLASH_ACR_ICEN) {
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regs->ACR &= ~FLASH_ACR_ICEN;
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/* Datasheet: ICRST: Instruction cache reset :
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* This bit can be written only when the instruction cache
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* is disabled
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*/
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regs->ACR |= FLASH_ACR_ICRST;
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regs->ACR &= ~FLASH_ACR_ICRST;
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regs->ACR |= FLASH_ACR_ICEN;
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}
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}
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static int write_dword(const struct device *dev, off_t offset, uint64_t val)
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{
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volatile uint32_t *flash = (uint32_t *)(offset + CONFIG_FLASH_BASE_ADDRESS);
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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uint32_t tmp;
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int ret, rc;
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uint32_t cpu1_sem_status;
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uint32_t cpu2_sem_status = 0;
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uint32_t key;
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/* if the control register is locked, do not fail silently */
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if (regs->CR & FLASH_CR_LOCK) {
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return -EIO;
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}
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/* Check if this double word is erased */
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if (flash[0] != 0xFFFFFFFFUL ||
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flash[1] != 0xFFFFFFFFUL) {
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return -EIO;
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}
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ret = flash_stm32_check_status(dev);
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if (ret < 0) {
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return -EIO;
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}
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/* Implementation of STM32 AN5289, proposed in STM32WB Cube Application
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* BLE_RfWithFlash
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* https://github.com/STMicroelectronics/STM32CubeWB/tree/master/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_RfWithFlash
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*/
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do {
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/**
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* When the PESD bit mechanism is used by CPU2 to protect its
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* timing, the PESD bit should be polled here.
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* If the PESD is set, the CPU1 will be stalled when reading
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* literals from an ISR that may occur after the flash
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* processing has been requested but suspended due to the PESD
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* bit.
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*
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* Note: This code is required only when the PESD mechanism is
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* used to protect the CPU2 timing.
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* However, keeping that code make it compatible with both
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* mechanisms.
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*/
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while (LL_FLASH_IsActiveFlag_OperationSuspended())
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;
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/* Enter critical section */
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key = irq_lock();
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/**
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* Depending on the application implementation, in case a
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* multitasking is possible with an OS, it should be checked
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* here if another task in the application disallowed flash
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* processing to protect some latency in critical code
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* execution.
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* When flash processing is ongoing, the CPU cannot access the
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* flash anymore.Trying to access the flash during that time
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* stalls the CPU.
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* The only way for CPU1 to disallow flash processing is to
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* take CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID.
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*/
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cpu1_sem_status = LL_HSEM_GetStatus(HSEM,
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CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID);
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if (cpu1_sem_status == 0) {
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/**
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* Check now if the CPU2 disallows flash processing to
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* protect its timing. If the semaphore is locked, the
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* CPU2 does not allow flash processing
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*
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* Note: By default, the CPU2 uses the PESD mechanism
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* to protect its timing, therefore, it is useless to
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* get/release the semaphore.
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*
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* However, keeping that code make it compatible with
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* bothmechanisms.
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* The protection by semaphore is enabled on CPU2 side
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* with the command SHCI_C2_SetFlashActivityControl()
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*
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*/
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cpu2_sem_status = LL_HSEM_1StepLock(HSEM,
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CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID);
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if (cpu2_sem_status == 0) {
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/**
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* When CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID is
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* taken, it is allowed to only write one
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* single 64bits data.
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* When several 64bits data need to be erased,
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* the application shall first exit from the
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* critical section and try again.
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*/
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/* Set the PG bit */
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regs->CR |= FLASH_CR_PG;
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/* Flush the register write */
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tmp = regs->CR;
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/* Perform the data write operation at desired
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* memory address
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*/
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flash[0] = (uint32_t)val;
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flash[1] = (uint32_t)(val >> 32);
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/**
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* Release the semaphore to give the
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* opportunity to CPU2 to protect its timing
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* versus the next flash operation by taking
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* this semaphore.
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* Note that the CPU2 is polling on this
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* semaphore so CPU1 shall release it as fast
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* as possible.
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* This is why this code is protected by a
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* critical section.
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*/
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LL_HSEM_ReleaseLock(HSEM,
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CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID,
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0);
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}
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}
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/* Exit critical section */
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irq_unlock(key);
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} while (cpu2_sem_status || cpu1_sem_status);
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/* Wait until the BSY bit is cleared */
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rc = flash_stm32_wait_flash_idle(dev);
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/* Clear the PG bit */
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regs->CR &= (~FLASH_CR_PG);
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return rc;
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}
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static int erase_page(const struct device *dev, uint32_t page)
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{
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uint32_t cpu1_sem_status;
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uint32_t cpu2_sem_status = 0;
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uint32_t key;
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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int rc;
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/* if the control register is locked, do not fail silently */
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if (regs->CR & FLASH_CR_LOCK) {
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return -EIO;
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}
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/* Check that no Flash memory operation is ongoing */
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rc = flash_stm32_wait_flash_idle(dev);
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if (rc < 0) {
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return rc;
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}
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/*
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* If an erase operation in Flash memory also concerns data in the data
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* or instruction cache, the user has to ensure that these data
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* are rewritten before they are accessed during code execution.
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*/
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flush_cache(regs);
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/* Implementation of STM32 AN5289, proposed in STM32WB Cube Application
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* BLE_RfWithFlash
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* https://github.com/STMicroelectronics/STM32CubeWB/tree/master/Projects/P-NUCLEO-WB55.Nucleo/Applications/BLE/BLE_RfWithFlash
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*/
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do {
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/**
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* When the PESD bit mechanism is used by CPU2 to protect its
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* timing, the PESD bit should be polled here.
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* If the PESD is set, the CPU1 will be stalled when reading
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* literals from an ISR that may occur after the flash
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* processing has been requested but suspended due to the PESD
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* bit.
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*
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* Note: This code is required only when the PESD mechanism is
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* used to protect the CPU2 timing.
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* However, keeping that code make it compatible with both
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* mechanisms.
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*/
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while (LL_FLASH_IsActiveFlag_OperationSuspended())
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;
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/* Enter critical section */
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key = irq_lock();
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/**
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* Depending on the application implementation, in case a
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* multitasking is possible with an OS, it should be checked
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* here if another task in the application disallowed flash
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* processing to protect some latency in critical code
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* execution.
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* When flash processing is ongoing, the CPU cannot access the
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* flash anymore.Trying to access the flash during that time
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* stalls the CPU.
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* The only way for CPU1 to disallow flash processing is to
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* take CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID.
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*/
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cpu1_sem_status = LL_HSEM_GetStatus(HSEM,
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CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID);
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if (cpu1_sem_status == 0) {
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/**
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* Check now if the CPU2 disallows flash processing to
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* protect its timing. If the semaphore is locked, the
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* CPU2 does not allow flash processing
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*
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* Note: By default, the CPU2 uses the PESD mechanism
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* to protect its timing, therefore, it is useless to
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* get/release the semaphore.
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*
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* However, keeping that code make it compatible with
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* bothmechanisms.
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* The protection by semaphore is enabled on CPU2 side
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* with the command SHCI_C2_SetFlashActivityControl()
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*
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*/
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cpu2_sem_status = LL_HSEM_1StepLock(HSEM,
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CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID);
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if (cpu2_sem_status == 0) {
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/**
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* When CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID is
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* taken, it is allowed to only erase one
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* sector.
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* When several sectors need to be erased,
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* the application shall first exit from the
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* critical section and try again.
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*/
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regs->CR |= FLASH_CR_PER;
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regs->CR &= ~FLASH_CR_PNB_Msk;
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regs->CR |= page << FLASH_CR_PNB_Pos;
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regs->CR |= FLASH_CR_STRT;
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/**
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* Release the semaphore to give the
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* opportunity to CPU2 to protect its timing
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* versus the next flash operation by taking
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* this semaphore.
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* Note that the CPU2 is polling on this
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* semaphore so CPU1 shall release it as fast
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* as possible.
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* This is why this code is protected by a
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* critical section.
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*/
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LL_HSEM_ReleaseLock(HSEM,
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CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID,
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0);
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}
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}
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/* Exit critical section */
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irq_unlock(key);
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} while (cpu2_sem_status || cpu1_sem_status);
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/* Wait for the BSY bit */
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rc = flash_stm32_wait_flash_idle(dev);
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regs->CR &= ~FLASH_CR_PER;
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return rc;
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}
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int flash_stm32_block_erase_loop(const struct device *dev,
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unsigned int offset,
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unsigned int len)
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{
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int i, rc = 0;
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#if defined(CONFIG_BT)
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/**
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* Notify the CPU2 that some flash erase activity may be executed
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* On reception of this command, the CPU2 enables the BLE timing
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* protection versus flash erase processing.
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* The Erase flash activity will be executed only when the BLE RF is
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* idle for at least 25ms.
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* The CPU2 will prevent all flash activity (write or erase) in all
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* cases when the BL RF Idle is shorter than 25ms.
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*/
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SHCI_C2_FLASH_EraseActivity(ERASE_ACTIVITY_ON);
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#endif /* CONFIG_BT */
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i = get_page(offset);
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for (; i <= get_page(offset + len - 1) ; ++i) {
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rc = erase_page(dev, i);
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if (rc < 0) {
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break;
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}
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}
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#if defined(CONFIG_BT)
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/**
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* Notify the CPU2 there will be no request anymore to erase the flash
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* On reception of this command, the CPU2 disables the BLE timing
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* protection versus flash erase processing
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*/
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SHCI_C2_FLASH_EraseActivity(ERASE_ACTIVITY_OFF);
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#endif /* CONFIG_BT */
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return rc;
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}
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int flash_stm32_write_range(const struct device *dev, unsigned int offset,
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const void *data, unsigned int len)
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{
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int i, rc = 0;
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for (i = 0; i < len; i += 8, offset += 8U) {
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rc = write_dword(dev, offset,
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UNALIGNED_GET((const uint64_t *) data + (i >> 3)));
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if (rc < 0) {
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return rc;
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}
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}
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return rc;
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}
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void flash_stm32_page_layout(const struct device *dev,
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const struct flash_pages_layout **layout,
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size_t *layout_size)
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{
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static struct flash_pages_layout stm32wb_flash_layout = {
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.pages_count = 0,
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.pages_size = 0,
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};
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ARG_UNUSED(dev);
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if (stm32wb_flash_layout.pages_count == 0) {
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stm32wb_flash_layout.pages_count = FLASH_SIZE / FLASH_PAGE_SIZE;
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stm32wb_flash_layout.pages_size = FLASH_PAGE_SIZE;
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}
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*layout = &stm32wb_flash_layout;
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*layout_size = 1;
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}
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int flash_stm32_check_status(const struct device *dev)
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{
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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uint32_t error = 0;
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/* Save Flash errors */
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error = (regs->SR & FLASH_FLAG_SR_ERRORS);
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error |= (regs->ECCR & FLASH_FLAG_ECCC);
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/* Clear systematic Option and Enginneering bits validity error */
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if (error & FLASH_FLAG_OPTVERR) {
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regs->SR |= FLASH_FLAG_SR_ERRORS;
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return 0;
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}
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if (error) {
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return -EIO;
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}
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return 0;
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}
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