553 lines
14 KiB
C
553 lines
14 KiB
C
/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <errno.h>
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#include <nanokernel.h>
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#include <gpio.h>
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#include "gpio_dw.h"
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#include "gpio_utils.h"
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#include "gpio_api_compat.h"
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#include <board.h>
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#include <sys_io.h>
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#include <init.h>
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#include <misc/util.h>
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#include <misc/__assert.h>
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#include <clock_control.h>
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#ifdef CONFIG_SHARED_IRQ
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#include <shared_irq.h>
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#endif
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#ifdef CONFIG_IOAPIC
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#include <drivers/ioapic.h>
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#endif
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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#include <power.h>
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#endif
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/*
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* ARC architecture configure IP through IO auxiliary registers.
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* Other architectures as ARM and x86 configure IP through MMIO registers
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*/
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#ifdef GPIO_DW_IO_ACCESS
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static inline uint32_t dw_read(uint32_t base_addr, uint32_t offset)
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{
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return sys_in32(base_addr + offset);
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}
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static inline void dw_write(uint32_t base_addr, uint32_t offset,
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uint32_t val)
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{
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sys_out32(val, base_addr + offset);
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}
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static void dw_set_bit(uint32_t base_addr, uint32_t offset,
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uint32_t bit, uint8_t value)
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{
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if (!value) {
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sys_io_clear_bit(base_addr + offset, bit);
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} else {
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sys_io_set_bit(base_addr + offset, bit);
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}
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}
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#else
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static inline uint32_t dw_read(uint32_t base_addr, uint32_t offset)
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{
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return sys_read32(base_addr + offset);
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}
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static inline void dw_write(uint32_t base_addr, uint32_t offset,
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uint32_t val)
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{
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sys_write32(val, base_addr + offset);
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}
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static void dw_set_bit(uint32_t base_addr, uint32_t offset,
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uint32_t bit, uint8_t value)
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{
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if (!value) {
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sys_clear_bit(base_addr + offset, bit);
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} else {
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sys_set_bit(base_addr + offset, bit);
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}
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}
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#endif
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#ifdef CONFIG_GPIO_DW_CLOCK_GATE
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static inline void _gpio_dw_clock_config(struct device *port)
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{
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char *drv = CONFIG_GPIO_DW_CLOCK_GATE_DRV_NAME;
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struct device *clk;
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clk = device_get_binding(drv);
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if (clk) {
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struct gpio_dw_runtime *context = port->driver_data;
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context->clock = clk;
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}
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}
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static inline void _gpio_dw_clock_on(struct device *port)
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{
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struct gpio_dw_config *config = port->config->config_info;
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struct gpio_dw_runtime *context = port->driver_data;
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clock_control_on(context->clock, config->clock_data);
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}
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static inline void _gpio_dw_clock_off(struct device *port)
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{
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struct gpio_dw_config *config = port->config->config_info;
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struct gpio_dw_runtime *context = port->driver_data;
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clock_control_off(context->clock, config->clock_data);
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}
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#else
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#define _gpio_dw_clock_config(...)
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#define _gpio_dw_clock_on(...)
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#define _gpio_dw_clock_off(...)
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#endif
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#ifdef CONFIG_SOC_QUARK_SE_SS
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static inline void dw_set_both_edges(uint32_t base_addr, uint32_t pin)
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{
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ARG_UNUSED(base_addr);
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ARG_UNUSED(pin);
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}
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#else
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static inline void dw_set_both_edges(uint32_t base_addr, uint32_t pin)
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{
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dw_set_bit(base_addr, INT_BOTHEDGE, pin, 1);
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}
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#endif
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static inline void dw_interrupt_config(struct device *port, int access_op,
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uint32_t pin, int flags)
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{
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struct gpio_dw_config *config = port->config->config_info;
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uint32_t base_addr = config->base_addr;
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uint8_t flag_is_set;
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/* set as an input pin */
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dw_set_bit(base_addr, SWPORTA_DDR, pin, 0);
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/* level or edge */
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flag_is_set = (flags & GPIO_INT_EDGE);
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dw_set_bit(base_addr, INTTYPE_LEVEL, pin, flag_is_set);
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/* Active low/high */
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flag_is_set = (flags & GPIO_INT_ACTIVE_HIGH);
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dw_set_bit(base_addr, INT_POLARITY, pin, flag_is_set);
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/* both edges */
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flag_is_set = (flags & GPIO_INT_DOUBLE_EDGE);
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if (flag_is_set) {
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dw_set_both_edges(base_addr, pin);
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dw_set_bit(base_addr, INTTYPE_LEVEL, pin, flag_is_set);
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}
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/* use built-in debounce */
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flag_is_set = (flags & GPIO_INT_DEBOUNCE);
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dw_set_bit(base_addr, PORTA_DEBOUNCE, pin, flag_is_set);
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/* Finally enabling interrupt */
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dw_set_bit(base_addr, INTEN, pin, 1);
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}
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static inline void dw_pin_config(struct device *port,
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uint32_t pin, int flags)
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{
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struct gpio_dw_config *config = port->config->config_info;
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uint32_t base_addr = config->base_addr;
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/* clear interrupt enable */
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dw_set_bit(base_addr, INTEN, pin, 0);
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/* set direction */
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dw_set_bit(base_addr, SWPORTA_DDR, pin, (flags & GPIO_DIR_MASK));
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if (flags & GPIO_INT) {
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dw_interrupt_config(port, GPIO_ACCESS_BY_PIN, pin, flags);
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}
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}
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static inline void dw_port_config(struct device *port, int flags)
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{
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struct gpio_dw_config *config = port->config->config_info;
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int i;
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for (i = 0; i < config->bits; i++) {
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dw_pin_config(port, i, flags);
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}
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}
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static inline int gpio_dw_config(struct device *port, int access_op,
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uint32_t pin, int flags)
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{
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if (((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) ||
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((flags & GPIO_DIR_IN) && (flags & GPIO_DIR_OUT))) {
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return -1;
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}
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if (GPIO_ACCESS_BY_PIN == access_op) {
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dw_pin_config(port, pin, flags);
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} else {
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dw_port_config(port, flags);
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}
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return 0;
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}
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static inline int gpio_dw_write(struct device *port, int access_op,
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uint32_t pin, uint32_t value)
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{
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struct gpio_dw_config *config = port->config->config_info;
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uint32_t base_addr = config->base_addr;
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if (GPIO_ACCESS_BY_PIN == access_op) {
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dw_set_bit(base_addr, SWPORTA_DR, pin, value);
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} else {
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dw_write(base_addr, SWPORTA_DR, value);
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}
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return 0;
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}
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static inline int gpio_dw_read(struct device *port, int access_op,
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uint32_t pin, uint32_t *value)
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{
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struct gpio_dw_config *config = port->config->config_info;
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uint32_t base_addr = config->base_addr;
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*value = dw_read(base_addr, EXT_PORTA);
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if (GPIO_ACCESS_BY_PIN == access_op) {
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*value = !!(*value & BIT(pin));
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}
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return 0;
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}
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static inline int gpio_dw_manage_callback(struct device *port,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_dw_runtime *context = port->driver_data;
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_gpio_manage_callback(&context->callbacks, callback, set);
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return 0;
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}
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static inline int gpio_dw_enable_callback(struct device *port, int access_op,
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uint32_t pin)
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{
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struct gpio_dw_config *config = port->config->config_info;
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uint32_t base_addr = config->base_addr;
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if (GPIO_ACCESS_BY_PIN == access_op) {
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dw_write(base_addr, PORTA_EOI, BIT(pin));
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dw_set_bit(base_addr, INTMASK, pin, 0);
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_gpio_enable_callback(port, BIT(pin));
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} else {
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dw_write(base_addr, PORTA_EOI, BIT_MASK(config->bits));
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dw_write(base_addr, INTMASK, 0);
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_gpio_enable_callback(port, BIT_MASK(config->bits));
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}
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return 0;
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}
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static inline int gpio_dw_disable_callback(struct device *port, int access_op,
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uint32_t pin)
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{
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struct gpio_dw_config *config = port->config->config_info;
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uint32_t base_addr = config->base_addr;
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if (GPIO_ACCESS_BY_PIN == access_op) {
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dw_set_bit(base_addr, INTMASK, pin, 1);
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_gpio_disable_callback(port, BIT(pin));
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} else {
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dw_write(base_addr, INTMASK, BIT_MASK(config->bits));
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_gpio_disable_callback(port, BIT_MASK(config->bits));
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}
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return 0;
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}
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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static inline int gpio_dw_suspend_port(struct device *port, int pm_policy)
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{
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_gpio_dw_clock_off(port);
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return 0;
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}
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static inline int gpio_dw_resume_port(struct device *port, int pm_policy)
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{
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_gpio_dw_clock_on(port);
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return 0;
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}
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#endif
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#if defined(CONFIG_SOC_QUARK_SE) || defined(CONFIG_SOC_QUARK_D2000)
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static inline void gpio_dw_unmask_int(uint32_t mask_addr)
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{
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sys_write32(sys_read32(mask_addr) & INT_UNMASK_IA, mask_addr);
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}
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#elif CONFIG_SOC_QUARK_SE_SS
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static inline void gpio_dw_unmask_int(uint32_t mask_addr)
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{
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sys_write32(sys_read32(mask_addr) & INT_ENABLE_ARC, mask_addr);
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}
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#else
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#define gpio_dw_unmask_int(...)
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#endif
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void gpio_dw_isr(void *arg)
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{
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struct device *port = (struct device *)arg;
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struct gpio_dw_runtime *context = port->driver_data;
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struct gpio_dw_config *config = port->config->config_info;
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uint32_t base_addr = config->base_addr;
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uint32_t int_status;
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int_status = dw_read(base_addr, INTSTATUS);
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#ifdef CONFIG_SHARED_IRQ
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/* If using with shared IRQ, this function will be called
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* by the shared IRQ driver. So check here if the interrupt
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* is coming from the GPIO controller (or somewhere else).
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*/
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if (!int_status) {
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return;
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}
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#endif
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dw_write(base_addr, PORTA_EOI, int_status);
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_gpio_fire_callbacks(&context->callbacks, port, int_status);
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}
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static struct gpio_driver_api api_funcs = {
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.config = gpio_dw_config,
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.write = gpio_dw_write,
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.read = gpio_dw_read,
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.manage_callback = gpio_dw_manage_callback,
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.enable_callback = gpio_dw_enable_callback,
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.disable_callback = gpio_dw_disable_callback,
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};
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#ifdef CONFIG_PCI
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static inline int gpio_dw_setup(struct device *dev)
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{
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struct gpio_dw_config *config = dev->config->config_info;
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pci_bus_scan_init();
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if (!pci_bus_scan(&config->pci_dev)) {
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return 0;
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}
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#ifdef CONFIG_PCI_ENUMERATION
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config->base_addr = config->pci_dev.addr;
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config->irq_num = config->pci_dev.irq;
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#endif
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pci_enable_regs(&config->pci_dev);
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pci_show(&config->pci_dev);
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return 1;
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}
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#else
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#define gpio_dw_setup(_unused_) (1)
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#endif /* CONFIG_PCI */
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int gpio_dw_initialize(struct device *port)
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{
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struct gpio_dw_config *config = port->config->config_info;
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uint32_t base_addr;
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if (!gpio_dw_setup(port)) {
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port->driver_api = NULL;
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return -EPERM;
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}
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base_addr = config->base_addr;
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#ifdef CONFIG_SOC_QUARK_SE_SS
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/* Need to enable clock for GPIO controller */
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dw_set_bit(base_addr, INT_CLOCK_SYNC, CLK_ENA_POS, 1);
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#endif /* CONFIG_SOC_QUARK_SE_SS */
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/* interrupts in sync with system clock */
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dw_set_bit(base_addr, INT_CLOCK_SYNC, LS_SYNC_POS, 1);
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_gpio_dw_clock_config(port);
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/* mask and disable interrupts */
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dw_write(base_addr, INTMASK, ~(0));
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dw_write(base_addr, INTEN, 0);
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dw_write(base_addr, PORTA_EOI, ~(0));
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config->config_func(port);
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return 0;
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}
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/* Bindings to the plaform */
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#if CONFIG_GPIO_DW_0
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void gpio_config_0_irq(struct device *port);
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struct gpio_dw_config gpio_config_0 = {
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.base_addr = GPIO_DW_0_BASE_ADDR,
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.bits = GPIO_DW_0_BITS,
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#ifdef CONFIG_GPIO_DW_0_IRQ_DIRECT
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.irq_num = GPIO_DW_0_IRQ,
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#endif
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#if CONFIG_PCI
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.pci_dev.class_type = GPIO_DW_PCI_CLASS,
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.pci_dev.bus = GPIO_DW_0_PCI_BUS,
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.pci_dev.dev = GPIO_DW_0_PCI_DEV,
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.pci_dev.vendor_id = GPIO_DW_PCI_VENDOR_ID,
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.pci_dev.device_id = GPIO_DW_PCI_DEVICE_ID,
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.pci_dev.function = GPIO_DW_0_PCI_FUNCTION,
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.pci_dev.bar = GPIO_DW_0_PCI_BAR,
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#endif
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.config_func = gpio_config_0_irq,
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#ifdef CONFIG_GPIO_DW_0_IRQ_SHARED
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.shared_irq_dev_name = CONFIG_GPIO_DW_0_IRQ_SHARED_NAME,
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#endif
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#ifdef CONFIG_GPIO_DW_CLOCK_GATE
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.clock_data = UINT_TO_POINTER(CONFIG_GPIO_DW_0_CLOCK_GATE_SUBSYS),
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#endif
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};
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struct gpio_dw_runtime gpio_0_runtime;
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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struct device_pm_ops gpio_dev_pm_ops = {
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.suspend = gpio_dw_suspend_port,
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.resume = gpio_dw_resume_port
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};
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DEVICE_AND_API_INIT_PM(gpio_dw_0, CONFIG_GPIO_DW_0_NAME, gpio_dw_initialize,
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&gpio_dev_pm_ops, &gpio_0_runtime, &gpio_config_0,
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SECONDARY, CONFIG_GPIO_DW_INIT_PRIORITY,
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&api_funcs);
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#else
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DEVICE_AND_API_INIT(gpio_dw_0, CONFIG_GPIO_DW_0_NAME, gpio_dw_initialize,
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&gpio_0_runtime, &gpio_config_0,
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SECONDARY, CONFIG_GPIO_DW_INIT_PRIORITY,
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&api_funcs);
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#endif
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GPIO_SETUP_COMPAT_DEV(gpio_dw_0);
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void gpio_config_0_irq(struct device *port)
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{
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struct gpio_dw_config *config = port->config->config_info;
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struct device *shared_irq_dev;
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#ifdef CONFIG_GPIO_DW_0_IRQ_DIRECT
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ARG_UNUSED(shared_irq_dev);
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IRQ_CONNECT(GPIO_DW_0_IRQ, CONFIG_GPIO_DW_0_IRQ_PRI, gpio_dw_isr,
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DEVICE_GET(gpio_dw_0), GPIO_DW_0_IRQ_FLAGS);
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irq_enable(config->irq_num);
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#elif defined(CONFIG_GPIO_DW_0_IRQ_SHARED)
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shared_irq_dev = device_get_binding(config->shared_irq_dev_name);
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__ASSERT(shared_irq_dev != NULL,
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"Failed to get gpio_dw_0 device binding");
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shared_irq_isr_register(shared_irq_dev, (isr_t)gpio_dw_isr, port);
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shared_irq_enable(shared_irq_dev, port);
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#endif
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gpio_dw_unmask_int(GPIO_DW_PORT_0_INT_MASK);
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}
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#endif /* CONFIG_GPIO_DW_0 */
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#if CONFIG_GPIO_DW_1
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void gpio_config_1_irq(struct device *port);
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struct gpio_dw_config gpio_dw_config_1 = {
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.base_addr = GPIO_DW_1_BASE_ADDR,
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.bits = GPIO_DW_1_BITS,
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#ifdef CONFIG_GPIO_DW_1_IRQ_DIRECT
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.irq_num = GPIO_DW_1_IRQ,
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#endif
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#if CONFIG_PCI
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.pci_dev.class_type = GPIO_DW_PCI_CLASS,
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.pci_dev.bus = GPIO_DW_1_PCI_BUS,
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.pci_dev.dev = GPIO_DW_1_PCI_DEV,
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.pci_dev.vendor_id = GPIO_DW_PCI_VENDOR_ID,
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.pci_dev.device_id = GPIO_DW_PCI_DEVICE_ID,
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.pci_dev.function = GPIO_DW_1_PCI_FUNCTION,
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.pci_dev.bar = GPIO_DW_1_PCI_BAR,
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#endif
|
|
.config_func = gpio_config_1_irq,
|
|
|
|
#ifdef CONFIG_GPIO_DW_1_IRQ_SHARED
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|
.shared_irq_dev_name = CONFIG_GPIO_DW_1_IRQ_SHARED_NAME,
|
|
#endif
|
|
#ifdef CONFIG_GPIO_DW_CLOCK_GATE
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|
.clock_data = UINT_TO_POINTER(CONFIG_GPIO_DW_1_CLOCK_GATE_SUBSYS),
|
|
#endif
|
|
};
|
|
|
|
struct gpio_dw_runtime gpio_1_runtime;
|
|
|
|
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
|
|
DEVICE_AND_API_INIT_PM(gpio_dw_1, CONFIG_GPIO_DW_1_NAME, gpio_dw_initialize,
|
|
&gpio_dev_pm_ops, &gpio_1_runtime, &gpio_dw_config_1,
|
|
SECONDARY, CONFIG_GPIO_DW_INIT_PRIORITY,
|
|
&api_funcs);
|
|
#else
|
|
DEVICE_AND_API_INIT(gpio_dw_1, CONFIG_GPIO_DW_1_NAME, gpio_dw_initialize,
|
|
&gpio_1_runtime, &gpio_dw_config_1,
|
|
SECONDARY, CONFIG_GPIO_DW_INIT_PRIORITY,
|
|
&api_funcs);
|
|
#endif
|
|
GPIO_SETUP_COMPAT_DEV(gpio_dw_1);
|
|
|
|
void gpio_config_1_irq(struct device *port)
|
|
{
|
|
struct gpio_dw_config *config = port->config->config_info;
|
|
struct device *shared_irq_dev;
|
|
|
|
#ifdef CONFIG_GPIO_DW_1_IRQ_DIRECT
|
|
ARG_UNUSED(shared_irq_dev);
|
|
IRQ_CONNECT(GPIO_DW_1_IRQ, CONFIG_GPIO_DW_1_IRQ_PRI, gpio_dw_isr,
|
|
DEVICE_GET(gpio_dw_1), GPIO_DW_1_IRQ_FLAGS);
|
|
irq_enable(config->irq_num);
|
|
#elif defined(CONFIG_GPIO_DW_1_IRQ_SHARED)
|
|
shared_irq_dev = device_get_binding(config->shared_irq_dev_name);
|
|
__ASSERT(shared_irq_dev != NULL,
|
|
"Failed to get gpio_dw_1 device binding");
|
|
shared_irq_isr_register(shared_irq_dev, (isr_t)gpio_dw_isr, port);
|
|
shared_irq_enable(shared_irq_dev, port);
|
|
#endif
|
|
gpio_dw_unmask_int(GPIO_DW_PORT_1_INT_MASK);
|
|
}
|
|
|
|
#endif /* CONFIG_GPIO_DW_1 */
|