33 lines
1.7 KiB
Plaintext
33 lines
1.7 KiB
Plaintext
/*
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define CONFIG_MCUX_CCM_BASE_ADDRESS NXP_IMX_CCM_400FC000_BASE_ADDRESS_0
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#define CONFIG_MCUX_CCM_NAME NXP_IMX_CCM_400FC000_LABEL
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#define CONFIG_MCUX_IGPIO_1_BASE_ADDRESS NXP_IMX_GPIO_401B8000_BASE_ADDRESS_0
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#define CONFIG_MCUX_IGPIO_1_NAME NXP_IMX_GPIO_401B8000_LABEL
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#define CONFIG_MCUX_IGPIO_1_IRQ_0 NXP_IMX_GPIO_401B8000_IRQ_0
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#define CONFIG_MCUX_IGPIO_1_IRQ_0_PRI NXP_IMX_GPIO_401B8000_IRQ_0_PRIORITY
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#define CONFIG_MCUX_IGPIO_1_IRQ_1 NXP_IMX_GPIO_401B8000_IRQ_1
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#define CONFIG_MCUX_IGPIO_1_IRQ_1_PRI NXP_IMX_GPIO_401B8000_IRQ_1_PRIORITY
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#define CONFIG_MCUX_IGPIO_5_BASE_ADDRESS NXP_IMX_GPIO_400C0000_BASE_ADDRESS_0
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#define CONFIG_MCUX_IGPIO_5_NAME NXP_IMX_GPIO_400C0000_LABEL
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#define CONFIG_MCUX_IGPIO_5_IRQ_0 NXP_IMX_GPIO_400C0000_IRQ_0
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#define CONFIG_MCUX_IGPIO_5_IRQ_0_PRI NXP_IMX_GPIO_400C0000_IRQ_0_PRIORITY
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#define CONFIG_MCUX_IGPIO_5_IRQ_1 NXP_IMX_GPIO_400C0000_IRQ_1
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#define CONFIG_MCUX_IGPIO_5_IRQ_1_PRI NXP_IMX_GPIO_400C0000_IRQ_1_PRIORITY
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#define CONFIG_UART_MCUX_LPUART_1_BASE_ADDRESS NXP_KINETIS_LPUART_40184000_BASE_ADDRESS_0
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#define CONFIG_UART_MCUX_LPUART_1_NAME NXP_KINETIS_LPUART_40184000_LABEL
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#define CONFIG_UART_MCUX_LPUART_1_IRQ NXP_KINETIS_LPUART_40184000_IRQ_0
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#define CONFIG_UART_MCUX_LPUART_1_IRQ_PRI NXP_KINETIS_LPUART_40184000_IRQ_0_PRIORITY
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#define CONFIG_UART_MCUX_LPUART_1_BAUD_RATE NXP_KINETIS_LPUART_40184000_CURRENT_SPEED
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#define CONFIG_UART_MCUX_LPUART_1_CLOCK_NAME NXP_IMX_CCM_400FC000_LABEL
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#define CONFIG_UART_MCUX_LPUART_1_CLOCK_SUBSYS NXP_KINETIS_LPUART_40184000_CCM_CLK_NAME_0
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