97 lines
2.8 KiB
C
97 lines
2.8 KiB
C
/*
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* Copyright (c) 2023 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <zephyr/spinlock.h>
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#include <zephyr/devicetree.h>
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#include <adsp_shim.h>
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#include <adsp_timestamp.h>
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#define TTS_BASE_ADDR DT_REG_ADDR(DT_NODELABEL(tts))
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#define TSCTRL_ADDR (TTS_BASE_ADDR + ADSP_TSCTRL_OFFSET)
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#define ISCS_ADDR (TTS_BASE_ADDR + ADSP_ISCS_OFFSET)
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#define LSCS_ADDR (TTS_BASE_ADDR + ADSP_LSCS_OFFSET)
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#define DWCCS_ADDR (TTS_BASE_ADDR + ADSP_DWCCS_OFFSET)
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#define ARTCS_ADDR (TTS_BASE_ADDR + ADSP_ARTCS_OFFSET)
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#define LWCCS_ADDR (TTS_BASE_ADDR + ADSP_LWCCS_OFFSET)
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/* Copies the bit-field specified by mask from src to dest */
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#define BITS_COPY(dest, src, mask) ((dest) = ((dest) & ~(mask)) | ((src) & (mask)))
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static struct k_spinlock lock;
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int intel_adsp_get_timestamp(uint32_t tsctrl, struct intel_adsp_timestamp *timestamp)
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{
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uint32_t trigger_mask = ADSP_SHIM_TSCTRL_HHTSE | ADSP_SHIM_TSCTRL_ODTS;
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uint32_t trigger_bits = tsctrl & trigger_mask;
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uint32_t tsctrl_temp;
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k_spinlock_key_t key;
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int ret = 0;
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/* Exactly one trigger bit must be set in a valid request */
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if (POPCOUNT(trigger_bits) != 1) {
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return -EINVAL;
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}
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key = k_spin_lock(&lock);
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tsctrl_temp = sys_read32(TSCTRL_ADDR);
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/* Abort if any timestamp capture in progress */
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if (tsctrl_temp & trigger_mask) {
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ret = -EBUSY;
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goto out;
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}
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/* Clear NTK (RW/1C) bit if needed */
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if (tsctrl_temp & ADSP_SHIM_TSCTRL_NTK) {
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sys_write32(tsctrl_temp, TSCTRL_ADDR);
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tsctrl_temp &= ~ADSP_SHIM_TSCTRL_NTK;
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}
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/* Setup the timestamping logic according to request */
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BITS_COPY(tsctrl_temp, tsctrl, ADSP_SHIM_TSCTRL_IONTE);
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BITS_COPY(tsctrl_temp, tsctrl, ADSP_SHIM_TSCTRL_DMATS);
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BITS_COPY(tsctrl_temp, tsctrl, ADSP_SHIM_TSCTRL_CLNKS);
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BITS_COPY(tsctrl_temp, tsctrl, ADSP_SHIM_TSCTRL_LWCS);
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BITS_COPY(tsctrl_temp, tsctrl, ADSP_SHIM_TSCTRL_CDMAS);
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sys_write32(tsctrl_temp, TSCTRL_ADDR);
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/* Start new timestamp capture by setting one of mutually exclusive
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* trigger bits.
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*/
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tsctrl_temp |= trigger_bits;
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sys_write32(tsctrl_temp, TSCTRL_ADDR);
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/* Wait for timestamp capture to complete */
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while (1) {
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tsctrl_temp = sys_read32(TSCTRL_ADDR);
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if (tsctrl_temp & ADSP_SHIM_TSCTRL_NTK) {
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break;
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}
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}
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/* Copy the timestamp data from HW registers to the snapshot buffer
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* provided by caller. As NTK bit is high at this stage, the timestamp
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* data in HW is guaranteed to be valid and static.
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*/
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timestamp->iscs = sys_read32(ISCS_ADDR);
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timestamp->lscs = sys_read64(LSCS_ADDR);
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timestamp->dwccs = sys_read64(DWCCS_ADDR);
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timestamp->artcs = sys_read64(ARTCS_ADDR);
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timestamp->lwccs = sys_read32(LWCCS_ADDR);
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/* Clear NTK (RW/1C) bit */
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tsctrl_temp |= ADSP_SHIM_TSCTRL_NTK;
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sys_write32(tsctrl_temp, TSCTRL_ADDR);
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out:
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k_spin_unlock(&lock, key);
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return ret;
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}
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