50 lines
1.8 KiB
C
50 lines
1.8 KiB
C
/*
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* Copyright (c) 2021 Andes Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __RISCV_ANDES_V5_SOC_V5_H_
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#define __RISCV_ANDES_V5_SOC_V5_H_
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/* Control and Status Registers (CSRs) available for Andes V5 SoCs */
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#define NDS_MMISC_CTL 0x7D0
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#define NDS_MCACHE_CTL 0x7CA
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#define NDS_MXSTATUS 0x7C4
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#define NDS_MCCTLBEGINADDR 0x7CB
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#define NDS_MCCTLCOMMAND 0x7CC
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#define NDS_MCCTLDATA 0x7CD
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#define NDS_UITB 0x800
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#define NDS_UCODE 0x801
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#define NDS_UCCTLBEGINADDR 0x80B
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#define NDS_UCCTLCOMMAND 0x80C
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#define NDS_MICM_CFG 0xFC0
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#define NDS_MDCM_CFG 0xFC1
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#define NDS_MMSC_CFG 0xFC2
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#define NDS_MMSC_CFG2 0xFC3
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#define NDS_MRVARCH_CFG 0xFCA
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/* Control and Status Registers (CSRs) available for Andes V5 PMA */
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#define NDS_PMACFG0 0xBC0
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#define NDS_PMACFG1 0xBC1
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#define NDS_PMACFG2 0xBC2
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#define NDS_PMACFG3 0xBC3
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#define NDS_PMAADDR0 0xBD0
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#define NDS_PMAADDR1 0xBD1
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#define NDS_PMAADDR2 0xBD2
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#define NDS_PMAADDR3 0xBD3
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#define NDS_PMAADDR4 0xBD4
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#define NDS_PMAADDR5 0xBD5
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#define NDS_PMAADDR6 0xBD6
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#define NDS_PMAADDR7 0xBD7
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#define NDS_PMAADDR8 0xBD8
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#define NDS_PMAADDR9 0xBD9
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#define NDS_PMAADDR10 0xBDA
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#define NDS_PMAADDR11 0xBDB
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#define NDS_PMAADDR12 0xBDC
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#define NDS_PMAADDR13 0xBDD
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#define NDS_PMAADDR14 0xBDE
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#define NDS_PMAADDR15 0xBDF
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#endif /* __RISCV_ANDES_V5_SOC_V5_H_ */
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