429 lines
10 KiB
C
429 lines
10 KiB
C
/*
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* Copyright (c) 2018 Savoir-Faire Linux.
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*
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* This driver is heavily inspired from the spi_flash_w25qxxdv.c SPI NOR driver.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <flash.h>
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#include <spi.h>
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#include <init.h>
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#include <string.h>
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#include "spi_nor.h"
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#include "flash_priv.h"
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#define SZ_256 0x100
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#define SZ_512 0x200
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#define SZ_1024 0x400
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#define SZ_4K 0x1000
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#define SZ_32K 0x8000
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#define SZ_64K 0x10000
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#define MASK_256 0xFF
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#define MASK_4K 0xFFF
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#define MASK_32K 0x7FFF
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#define MASK_64K 0xFFFF
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#define SPI_NOR_MAX_ADDR_WIDTH 4
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#define SECTORS_COUNT ((DT_JEDEC_SPI_NOR_0_SIZE / 8) \
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/ CONFIG_SPI_NOR_SECTOR_SIZE)
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#define JEDEC_ID(x) \
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{ \
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((x) >> 16) & 0xFF, \
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((x) >> 8) & 0xFF, \
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(x) & 0xFF, \
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}
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/**
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* struct spi_nor_data - Structure for defining the SPI NOR access
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* @spi: The SPI device
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* @spi_cfg: The SPI configuration
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* @cs_ctrl: The GPIO pin used to emulate the SPI CS if required
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* @sem: The semaphore to access to the flash
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*/
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struct spi_nor_data {
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struct device *spi;
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struct spi_config spi_cfg;
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#ifdef DT_JEDEC_SPI_NOR_0_CS_GPIO_CONTROLLER
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struct spi_cs_control cs_ctrl;
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#endif /* DT_JEDEC_SPI_NOR_0_CS_GPIO_CONTROLLER */
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struct k_sem sem;
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};
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#if defined(CONFIG_MULTITHREADING)
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#define SYNC_INIT() k_sem_init( \
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&((struct spi_nor_data *)dev->driver_data)->sem, 1, UINT_MAX)
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#define SYNC_LOCK() k_sem_take(&driver_data->sem, K_FOREVER)
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#define SYNC_UNLOCK() k_sem_give(&driver_data->sem)
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#else
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#define SYNC_INIT()
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#define SYNC_LOCK()
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#define SYNC_UNLOCK()
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#endif
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/*
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* @brief Send an SPI command
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*
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* @param dev Device struct
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* @param opcode The command to send
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* @param is_addressed A flag to define if the command is addressed
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* @param addr The address to send
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* @param data The buffer to store or read the value
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* @param length The size of the buffer
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* @param is_write A flag to define if it's a read or a write command
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* @return 0 on success, negative errno code otherwise
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*/
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static int spi_nor_access(const struct device *const dev,
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u8_t opcode, bool is_addressed, off_t addr,
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void *data, size_t length, bool is_write)
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{
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struct spi_nor_data *const driver_data = dev->driver_data;
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u8_t buf[4] = {
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opcode,
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(addr & 0xFF0000) >> 16,
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(addr & 0xFF00) >> 8,
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(addr & 0xFF),
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};
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struct spi_buf spi_buf[2] = {
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{
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.buf = buf,
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.len = (is_addressed) ? 4 : 1,
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},
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{
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.buf = data,
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.len = length
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}
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};
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const struct spi_buf_set tx_set = {
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.buffers = spi_buf,
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.count = (length) ? 2 : 1
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};
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const struct spi_buf_set rx_set = {
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.buffers = spi_buf,
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.count = 2
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};
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if (is_write) {
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return spi_write(driver_data->spi,
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&driver_data->spi_cfg, &tx_set);
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}
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return spi_transceive(driver_data->spi,
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&driver_data->spi_cfg, &tx_set, &rx_set);
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}
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#define spi_nor_cmd_read(dev, opcode, dest, length) \
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spi_nor_access(dev, opcode, false, 0, dest, length, false)
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#define spi_nor_cmd_addr_read(dev, opcode, addr, dest, length) \
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spi_nor_access(dev, opcode, true, addr, dest, length, false)
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#define spi_nor_cmd_write(dev, opcode) \
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spi_nor_access(dev, opcode, false, 0, NULL, 0, true)
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#define spi_nor_cmd_addr_write(dev, opcode, addr, src, length) \
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spi_nor_access(dev, opcode, true, addr, src, length, true)
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/**
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* @brief Retrieve the Flash JEDEC ID and compare it with the one expected
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*
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* @param dev The device structure
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* @param flash_id The flash info structure which contains the expected JEDEC ID
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* @return 0 on success, negative errno code otherwise
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*/
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static inline int spi_nor_read_id(struct device *dev,
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const struct spi_nor_config *const flash_id)
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{
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u8_t buf[SPI_NOR_MAX_ID_LEN];
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if (spi_nor_cmd_read(dev, SPI_NOR_CMD_RDID, buf,
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SPI_NOR_MAX_ID_LEN) != 0) {
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return -EIO;
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}
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if (memcmp(flash_id->id, buf, SPI_NOR_MAX_ID_LEN) != 0) {
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return -ENODEV;
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}
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return 0;
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}
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/**
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* @brief Wait until the flash is ready
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*
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* @param dev The device structure
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* @return 0 on success, negative errno code otherwise
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*/
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static int spi_nor_wait_until_ready(struct device *dev)
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{
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int ret;
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u8_t reg;
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do {
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ret = spi_nor_cmd_read(dev, SPI_NOR_CMD_RDSR, ®, 1);
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} while (!ret && (reg & SPI_NOR_WIP_BIT));
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return ret;
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}
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static int spi_nor_read(struct device *dev, off_t addr, void *dest,
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size_t size)
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{
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struct spi_nor_data *const driver_data = dev->driver_data;
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const struct spi_nor_config *params = dev->config->config_info;
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int ret;
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int to_read;
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/* should be between 0 and flash size */
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if ((addr < 0) || (addr + size) > (params->sector_size
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* params->n_sectors)) {
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return -EINVAL;
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}
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SYNC_LOCK();
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spi_nor_wait_until_ready(dev);
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while (size) {
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to_read = size;
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if (size > params->page_size) {
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to_read = params->page_size;
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}
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ret = spi_nor_cmd_addr_read(dev, SPI_NOR_CMD_READ, addr,
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dest, to_read);
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if (ret != 0) {
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SYNC_UNLOCK();
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return ret;
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}
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size -= to_read;
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addr += to_read;
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dest = (u8_t *)dest + to_read;
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}
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SYNC_UNLOCK();
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return 0;
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}
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static int spi_nor_write(struct device *dev, off_t addr, const void *src,
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size_t size)
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{
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struct spi_nor_data *const driver_data = dev->driver_data;
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const struct spi_nor_config *params = dev->config->config_info;
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int ret;
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size_t to_write;
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/* should be between 0 and flash size */
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if ((addr < 0) || ((size + addr) > (params->sector_size *
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params->n_sectors))) {
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return -EINVAL;
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}
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SYNC_LOCK();
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while (size) {
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/* write enable */
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spi_nor_cmd_write(dev, SPI_NOR_CMD_WREN);
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to_write = size;
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if (size >= params->page_size) {
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to_write = params->page_size;
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}
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ret = spi_nor_cmd_addr_write(dev, SPI_NOR_CMD_PP, addr,
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(void *)src, to_write);
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if (ret != 0) {
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SYNC_UNLOCK();
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return ret;
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}
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size -= to_write;
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addr += to_write;
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src = (u8_t *)src + to_write;
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spi_nor_wait_until_ready(dev);
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}
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SYNC_UNLOCK();
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return 0;
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}
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static int spi_nor_erase(struct device *dev, off_t addr, size_t size)
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{
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struct spi_nor_data *const driver_data = dev->driver_data;
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const struct spi_nor_config *params = dev->config->config_info;
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/* should be between 0 and flash size */
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if ((addr < 0) || ((size + addr) >
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(params->sector_size * params->n_sectors))) {
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return -ENODEV;
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}
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SYNC_LOCK();
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while (size) {
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/* write enable */
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spi_nor_cmd_write(dev, SPI_NOR_CMD_WREN);
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if (size == (params->sector_size * params->n_sectors)) {
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/* chip erase */
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spi_nor_cmd_write(dev, SPI_NOR_CMD_CE);
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size -= (params->sector_size * params->n_sectors);
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} else if ((DT_JEDEC_SPI_NOR_0_ERASE_BLOCK_SIZE == SZ_64K)
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&& (size >= SZ_64K)
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&& ((addr & MASK_64K) == 0)) {
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/* 64 KiB block erase */
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spi_nor_cmd_addr_write(dev, SPI_NOR_CMD_BE, addr,
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NULL, 0);
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addr += SZ_64K;
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size -= SZ_64K;
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} else if ((DT_JEDEC_SPI_NOR_0_ERASE_BLOCK_SIZE == SZ_32K)
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&& (size >= SZ_32K)
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&& ((addr & MASK_32K) == 0)) {
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/* 32 KiB block erase */
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spi_nor_cmd_addr_write(dev, SPI_NOR_CMD_BE_32K, addr,
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NULL, 0);
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addr += SZ_32K;
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size -= SZ_32K;
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} else if ((size >= params->sector_size) &&
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((addr & (params->sector_size - 1)) == 0)) {
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/* sector erase */
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spi_nor_cmd_addr_write(dev, SPI_NOR_CMD_SE, addr,
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NULL, 0);
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addr += params->sector_size;
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size -= params->sector_size;
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} else {
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/* minimal erase size is at least a sector size */
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SYNC_UNLOCK();
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return -EINVAL;
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}
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spi_nor_wait_until_ready(dev);
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}
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SYNC_UNLOCK();
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return 0;
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}
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static int spi_nor_write_protection_set(struct device *dev, bool write_protect)
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{
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struct spi_nor_data *const driver_data = dev->driver_data;
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int ret;
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SYNC_LOCK();
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spi_nor_wait_until_ready(dev);
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ret = spi_nor_cmd_write(dev, (write_protect) ?
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SPI_NOR_CMD_WRDI : SPI_NOR_CMD_WREN);
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SYNC_UNLOCK();
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return ret;
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}
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/**
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* @brief Configure the flash
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*
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* @param dev The flash device structure
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* @param info The flash info structure
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* @return 0 on success, negative errno code otherwise
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*/
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static int spi_nor_configure(struct device *dev)
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{
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struct spi_nor_data *data = dev->driver_data;
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const struct spi_nor_config *params = dev->config->config_info;
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data->spi = device_get_binding(DT_JEDEC_SPI_NOR_0_BUS_NAME);
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if (!data->spi) {
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return -EINVAL;
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}
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data->spi_cfg.frequency = DT_JEDEC_SPI_NOR_0_SPI_MAX_FREQUENCY;
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data->spi_cfg.operation = SPI_WORD_SET(8);
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data->spi_cfg.slave = DT_JEDEC_SPI_NOR_0_BASE_ADDRESS;
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#ifdef DT_JEDEC_SPI_NOR_0_CS_GPIO_CONTROLLER
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data->cs_ctrl.gpio_dev =
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device_get_binding(DT_JEDEC_SPI_NOR_0_CS_GPIO_CONTROLLER);
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if (!data->cs_ctrl.gpio_dev) {
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return -ENODEV;
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}
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data->cs_ctrl.gpio_pin = DT_JEDEC_SPI_NOR_0_CS_GPIO_PIN;
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data->cs_ctrl.delay = CONFIG_SPI_NOR_CS_WAIT_DELAY;
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data->spi_cfg.cs = &data->cs_ctrl;
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#endif /* DT_JEDEC_SPI_NOR_0_CS_GPIO_CONTROLLER */
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/* now the spi bus is configured, we can verify the flash id */
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if (spi_nor_read_id(dev, params) != 0) {
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return -ENODEV;
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}
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return 0;
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}
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/**
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* @brief Initialize and configure the flash
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*
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* @param name The flash name
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* @return 0 on success, negative errno code otherwise
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*/
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static int spi_nor_init(struct device *dev)
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{
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SYNC_INIT();
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return spi_nor_configure(dev);
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}
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#if defined(CONFIG_FLASH_PAGE_LAYOUT)
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static const struct flash_pages_layout dev_layout = {
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.pages_count = DT_JEDEC_SPI_NOR_0_SIZE / 8 / DT_JEDEC_SPI_NOR_0_ERASE_BLOCK_SIZE,
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.pages_size = DT_JEDEC_SPI_NOR_0_ERASE_BLOCK_SIZE,
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};
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static void spi_nor_pages_layout(struct device *dev,
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const struct flash_pages_layout **layout,
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size_t *layout_size)
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{
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*layout = &dev_layout;
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*layout_size = 1;
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}
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#endif /* CONFIG_FLASH_PAGE_LAYOUT */
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static const struct flash_driver_api spi_nor_api = {
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.read = spi_nor_read,
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.write = spi_nor_write,
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.erase = spi_nor_erase,
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.write_protection = spi_nor_write_protection_set,
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#if defined(CONFIG_FLASH_PAGE_LAYOUT)
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.page_layout = spi_nor_pages_layout,
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#endif
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.write_block_size = DT_JEDEC_SPI_NOR_0_WRITE_BLOCK_SIZE,
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};
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static const struct spi_nor_config flash_id = {
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.id = {
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DT_JEDEC_SPI_NOR_0_JEDEC_ID_0,
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DT_JEDEC_SPI_NOR_0_JEDEC_ID_1,
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DT_JEDEC_SPI_NOR_0_JEDEC_ID_2,
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},
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.page_size = CONFIG_SPI_NOR_PAGE_SIZE,
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.sector_size = CONFIG_SPI_NOR_SECTOR_SIZE,
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.n_sectors = SECTORS_COUNT,
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};
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static struct spi_nor_data spi_nor_memory_data;
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DEVICE_AND_API_INIT(spi_flash_memory, DT_JEDEC_SPI_NOR_0_LABEL,
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&spi_nor_init, &spi_nor_memory_data,
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&flash_id, POST_KERNEL, CONFIG_SPI_NOR_INIT_PRIORITY,
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&spi_nor_api);
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