365 lines
7.6 KiB
C
365 lines
7.6 KiB
C
/*
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* Copyright (c) 2017 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Include esp-idf headers first to avoid redefining BIT() macro */
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#include <soc/dport_reg.h>
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#include <soc/gpio_reg.h>
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#include <soc/io_mux_reg.h>
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#include <soc/soc.h>
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#include <soc.h>
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#include <errno.h>
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#include <device.h>
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#include <gpio.h>
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#include <kernel.h>
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#include <misc/util.h>
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#include <pinmux.h>
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#include "gpio_utils.h"
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struct gpio_esp32_data {
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struct device *pinmux;
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struct {
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struct {
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volatile u32_t *set_reg;
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volatile u32_t *clear_reg;
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} write;
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struct {
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volatile u32_t *reg;
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} read;
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struct {
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volatile u32_t *status_reg;
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volatile u32_t *ack_reg;
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} irq;
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int pin_offset;
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} port;
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u32_t cb_pins;
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sys_slist_t cb;
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};
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static int convert_int_type(int flags)
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{
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/* Reference: "ESP32 Technical Reference Manual", "IO_MUX and
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* GPIO matrix"; "GPIO_PINn_INT_TYPE".
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*/
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if (!(flags & GPIO_INT)) {
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return 0; /* Disables interrupt for a pin. */
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}
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if ((flags & GPIO_INT_EDGE) == GPIO_INT_EDGE) {
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if ((flags & GPIO_INT_ACTIVE_HIGH) == GPIO_INT_ACTIVE_HIGH) {
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return 1;
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}
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if ((flags & GPIO_INT_DOUBLE_EDGE) == GPIO_INT_DOUBLE_EDGE) {
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return 3;
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}
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return 2; /* Defaults to falling edge. */
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}
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if ((flags & GPIO_INT_EDGE) == GPIO_INT_LEVEL) {
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if ((flags & GPIO_INT_ACTIVE_HIGH) == GPIO_INT_ACTIVE_HIGH) {
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return 5;
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}
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return 4; /* Defaults to low level. */
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}
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/* Any other type of interrupt triggering is invalid. */
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return -EINVAL;
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}
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static inline u32_t *gpio_pin_reg(int pin)
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{
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return (u32_t *)(GPIO_PIN0_REG + pin * 4);
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}
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static int config_interrupt(u32_t pin, int flags)
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{
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volatile u32_t *reg = gpio_pin_reg(pin);
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int type = convert_int_type(flags);
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u32_t v;
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unsigned int key;
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if (type < 0) {
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return type;
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}
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key = irq_lock();
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v = *reg;
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v &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M);
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/* Bit 3 of INT_ENA will enable interrupts on CPU 0 */
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v |= (1<<2) << GPIO_PIN_INT_ENA_S;
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/* Interrupt triggering mode */
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v |= type << GPIO_PIN_INT_TYPE_S;
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*reg = v;
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irq_unlock(key);
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return 0;
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}
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static void config_polarity(u32_t pin, int flags)
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{
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volatile u32_t *reg = (u32_t *)(GPIO_FUNC0_IN_SEL_CFG_REG + 4 * pin);
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if (flags & GPIO_POL_INV) {
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*reg |= BIT(GPIO_FUNC0_IN_INV_SEL_S);
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} else {
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*reg &= ~BIT(GPIO_FUNC0_IN_INV_SEL_S);
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}
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}
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static void config_drive_strength(u32_t pin, int flags)
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{
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volatile u32_t *reg = gpio_pin_reg(pin);
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if ((flags & GPIO_DS_DISCONNECT_LOW) == GPIO_DS_DISCONNECT_LOW) {
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*reg |= GPIO_PIN_PAD_DRIVER;
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} else {
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*reg &= ~GPIO_PIN_PAD_DRIVER;
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}
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}
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static int gpio_esp32_config(struct device *dev, int access_op,
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u32_t pin, int flags)
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{
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struct gpio_esp32_data *data = dev->driver_data;
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u32_t func;
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int r;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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/* Query pinmux to validate pin number. */
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r = pinmux_pin_get(data->pinmux, pin, &func);
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if (r < 0) {
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return r;
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}
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pinmux_pin_set(data->pinmux, pin, PIN_FUNC_GPIO);
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if (flags & GPIO_PUD_PULL_UP) {
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pinmux_pin_pullup(data->pinmux, pin, PINMUX_PULLUP_ENABLE);
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} else if (flags & GPIO_PUD_PULL_DOWN) {
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pinmux_pin_pullup(data->pinmux, pin, PINMUX_PULLUP_DISABLE);
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}
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if (flags & GPIO_DIR_OUT) {
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r = pinmux_pin_input_enable(data->pinmux, pin,
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PINMUX_OUTPUT_ENABLED);
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assert(r >= 0);
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} else {
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pinmux_pin_input_enable(data->pinmux, pin,
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PINMUX_INPUT_ENABLED);
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config_polarity(pin, flags);
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}
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config_drive_strength(pin, flags);
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return config_interrupt(pin, flags);
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}
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static int gpio_esp32_write(struct device *dev, int access_op,
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u32_t pin, u32_t value)
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{
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struct gpio_esp32_data *data = dev->driver_data;
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u32_t v;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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v = BIT(pin - data->port.pin_offset);
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if (value) {
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*data->port.write.set_reg = v;
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} else {
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*data->port.write.clear_reg = v;
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}
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return 0;
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}
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static int gpio_esp32_read(struct device *dev, int access_op,
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u32_t pin, u32_t *value)
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{
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struct gpio_esp32_data *data = dev->driver_data;
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u32_t v;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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v = *data->port.read.reg;
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*value = !!(v & BIT(pin - data->port.pin_offset));
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return 0;
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}
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static int gpio_esp32_manage_callback(struct device *dev,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_esp32_data *data = dev->driver_data;
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return _gpio_manage_callback(&data->cb, callback, set);
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}
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static int gpio_esp32_enable_callback(struct device *dev,
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int access_op, u32_t pin)
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{
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struct gpio_esp32_data *data = dev->driver_data;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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data->cb_pins |= BIT(pin);
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return 0;
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}
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return -ENOTSUP;
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}
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static int gpio_esp32_disable_callback(struct device *dev,
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int access_op, u32_t pin)
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{
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struct gpio_esp32_data *data = dev->driver_data;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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data->cb_pins &= ~BIT(pin);
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return 0;
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}
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return -ENOTSUP;
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}
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static void gpio_esp32_fire_callbacks(struct device *device)
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{
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struct gpio_esp32_data *data = device->driver_data;
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u32_t values = *data->port.irq.status_reg;
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if (values & data->cb_pins) {
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_gpio_fire_callbacks(&data->cb, device, values);
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}
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*data->port.irq.ack_reg = values;
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}
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static void gpio_esp32_isr(void *param);
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static int gpio_esp32_init(struct device *device)
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{
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struct gpio_esp32_data *data = device->driver_data;
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static bool isr_connected;
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data->pinmux = device_get_binding(CONFIG_PINMUX_NAME);
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if (!data->pinmux) {
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return -ENOTSUP;
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}
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if (!isr_connected) {
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irq_disable(CONFIG_GPIO_ESP32_IRQ);
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IRQ_CONNECT(CONFIG_GPIO_ESP32_IRQ, 1, gpio_esp32_isr,
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NULL, 0);
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esp32_rom_intr_matrix_set(0, ETS_GPIO_INTR_SOURCE,
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CONFIG_GPIO_ESP32_IRQ);
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irq_enable(CONFIG_GPIO_ESP32_IRQ);
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isr_connected = true;
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}
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return 0;
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}
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static const struct gpio_driver_api gpio_esp32_driver = {
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.config = gpio_esp32_config,
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.write = gpio_esp32_write,
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.read = gpio_esp32_read,
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.manage_callback = gpio_esp32_manage_callback,
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.enable_callback = gpio_esp32_enable_callback,
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.disable_callback = gpio_esp32_disable_callback,
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};
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#if defined(CONFIG_GPIO_ESP32_0)
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static struct gpio_esp32_data gpio_data_pins_0_to_31 = {
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.port = {
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.write = {
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.set_reg = (u32_t *)GPIO_OUT_W1TS_REG,
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.clear_reg = (u32_t *)GPIO_OUT_W1TC_REG,
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},
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.read = {
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.reg = (u32_t *)GPIO_IN_REG,
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},
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.irq = {
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.status_reg = (u32_t *)GPIO_STATUS_REG,
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.ack_reg = (u32_t *)GPIO_STATUS_W1TC_REG,
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},
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.pin_offset = 0,
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}
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};
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#endif
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#if defined(CONFIG_GPIO_ESP32_1)
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static struct gpio_esp32_data gpio_data_pins_32_to_39 = {
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.port = {
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.write = {
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.set_reg = (u32_t *)GPIO_OUT1_W1TS_REG,
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.clear_reg = (u32_t *)GPIO_OUT1_W1TC_REG,
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},
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.read = {
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.reg = (u32_t *)GPIO_IN1_REG,
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},
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.irq = {
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.status_reg = (u32_t *)GPIO_STATUS1_REG,
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.ack_reg = (u32_t *)GPIO_STATUS1_W1TC_REG,
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},
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.pin_offset = 32,
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}
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};
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#endif
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#define GPIO_DEVICE_INIT(__name, __data_struct_name) \
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DEVICE_AND_API_INIT(gpio_esp32_ ## __data_struct_name, \
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__name, \
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gpio_esp32_init, \
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&gpio_data_pins_ ## __data_struct_name, \
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NULL, \
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POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&gpio_esp32_driver)
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/* GPIOs are divided in two groups for ESP32 because the callback
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* API works with 32-bit bitmasks to manage interrupt callbacks,
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* and the device has 40 GPIO pins.
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*/
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#if defined(CONFIG_GPIO_ESP32_0)
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GPIO_DEVICE_INIT(CONFIG_GPIO_ESP32_0_NAME, 0_to_31);
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#endif
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#if defined(CONFIG_GPIO_ESP32_1)
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GPIO_DEVICE_INIT(CONFIG_GPIO_ESP32_1_NAME, 32_to_39);
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#endif
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static void gpio_esp32_isr(void *param)
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{
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#if defined(CONFIG_GPIO_ESP32_0)
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gpio_esp32_fire_callbacks(DEVICE_GET(gpio_esp32_0_to_31));
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#endif
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#if defined(CONFIG_GPIO_ESP32_1)
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gpio_esp32_fire_callbacks(DEVICE_GET(gpio_esp32_32_to_39));
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#endif
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ARG_UNUSED(param);
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}
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