85 lines
2.4 KiB
YAML
85 lines
2.4 KiB
YAML
# Copyright (c) 2023 SLB
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Infineon XMC4XXX PWM Capture Compare Unit 4 (CCU4) module
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The are four CCU4 modules with dts node labels:
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pwm_ccu40, pwm_ccu41, pwm_ccu42, pwm_ccu43.
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Each module has four slices and each slice has one channel.
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A channel is connected to a particular gpio pin, which are defined
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using pinctrl in:
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dts/arm/infineon/xmc4xxx_xxx-pinctrl.dtsi
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The CCU4 modules uses the CCU clock source. Each slice applies a separate
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prescalar which divides the clock.
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Device tree example:
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A node can define a 'pwm' field, usually referenced in a 'pwms'
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property, where the entries include the PWM module phandle,
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channel number, pulse period (in nanoseconds or set using
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PWM_XX() macros), and a channela
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flag (PWM_POLARITY_NORMAL/PWM_POLARITY_INVERTED).
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The pwm ccu4 node must define the slice-prescaler values and the pinctrl nodes:
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&pwm_ccu40 {
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slice-prescaler = <15 15 15 15>;
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pinctrl-0 = <&pwm_out_p1_1_ccu40_ch2>;
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pinctrl-names = "default";
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};
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Another node can reference the PWM as follows:
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&test_node {
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...
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pwms = <&pwm_ccu40 0 PWM_SEC(1) PWM_POLARITY_NORMAL>;
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...
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};
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The user must also explicitly set pinctrl properties.
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The pin should be configured with drive-push-pull bool option and hwctrl should be set
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to disabled. The drive-strength field can be set to any of the supported values:
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&pwm_out_p1_1_ccu40_ch2 {
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drive-strength = "strong-medium-edge";
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drive-push-pull;
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hwctrl = "disabled";
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};
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The CCU4 pinctrl nodes have a node labels in the format
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pwm_out_p{PORT}_{PIN}_ccu4{MODULE_IDX}_ch{CHANNEL_IDX}, where MODULE_IDX and
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CHANNEL_IDX refers to specific pwm_ccu4x module and channel, respectively.
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PORT/PIN pair defines what gpio the channel connects to.
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compatible: "infineon,xmc4xxx-ccu4-pwm"
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include:
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- name: base.yaml
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- name: pwm-controller.yaml
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- name: pinctrl-device.yaml
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properties:
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reg:
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required: true
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pinctrl-0:
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required: true
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pinctrl-names:
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required: true
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slice-prescaler:
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type: array
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required: true
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description: |
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Defines the clock divider for each channel.
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The entry in the array will divide CCU clock by (2 << value).
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The range for the prescaler values is [0, 15].
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Reducing prescaler value will improve resolution but decrease the maximum period.
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"#pwm-cells":
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const: 3
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pwm-cells:
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- channel
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- period
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- flags
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