71 lines
1.6 KiB
YAML
71 lines
1.6 KiB
YAML
# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or
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# an affiliate of Cypress Semiconductor Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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description: Infineon Cat1 PWM
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compatible: "infineon,cat1-pwm"
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include: [pwm-controller.yaml, pinctrl-device.yaml]
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properties:
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reg:
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type: array
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required: true
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interrupts:
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type: array
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required: true
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pinctrl-0:
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description: |
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PORT pin configuration for the PWM signal.
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We expect that the phandles will reference pinctrl nodes. These
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nodes will have a nodelabel that matches the Infineon SoC Pinctrl
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defines and have following
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format: p<port>_<pin>_<peripheral inst>_<signal>.
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Examples:
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pinctrl-0 = <&p1_1_pwm0_0>;
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required: true
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pinctrl-names:
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required: true
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resolution:
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type: int
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divider-type:
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type: int
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description: |
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Specifies which type of divider to use.
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Defined by cy_en_divider_types_t in cy_sysclk.h.
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required: true
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divider-sel:
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type: int
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description: |
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Specifies which divider of the selected type to configure.
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required: true
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divider-val:
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type: int
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description: |
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Causes integer division of (divider value + 1), or division by 1 to 256
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(8-bit divider) or 1 to 65536 (16-bit divider).
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required: true
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"#pwm-cells":
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const: 3
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description: |
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Number of items to expect in a PWM
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- channel of the timer used for PWM (not used)
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- period to set in ns
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- flags: standard flags like PWM_POLARITY_NORMAL
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pwm-cells:
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- channel
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- period
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- flags
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