116 lines
3.8 KiB
YAML
116 lines
3.8 KiB
YAML
# Copyright 2023 NXP
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# SPDX-License-Identifier: Apache-2.0
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description: |
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NXP S32 pinctrl node for S32K3 SoCs.
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The NXP S32 pin controller is a singleton node responsible for controlling
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the pin function selection and pin properties. This node, labeled 'pinctrl' in
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the SoC's devicetree, will define pin configurations in pin groups. Each group
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within the pin configuration defines the pin configuration for a peripheral,
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and each numbered subgroup in the pin group defines all the pins for that
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peripheral with the same configuration properties. The 'pinmux' property in
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a group selects the pins to be configured, and the remaining properties set
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configuration values for those pins.
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For example, to configure the pinmux for UART0, modify the 'pinctrl' from your
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board or application devicetree overlay as follows:
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/* Include the SoC package header containing the predefined pins definitions */
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#include <nxp/s32/S32K344-257BGA-pinctrl.h>
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&pinctrl {
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uart0_default: uart0_default {
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group1 {
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pinmux = <PTA3_LPUART0_TX_O>;
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output-enable;
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};
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group2 {
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pinmux = <PTA28_LPUART0_RX>;
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input-enable;
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};
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};
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};
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The 'uart0_default' node contains the pin configurations for a particular state
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of a device. The 'default' state is the active state. Other states for the same
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device can be specified in separate child nodes of 'pinctrl'.
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In addition to 'pinmux' property, each group can contain other properties such as
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'bias-pull-up' or 'slew-rate' that will be applied to all the pins defined in
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'pinmux' array. To enable the input buffer use 'input-enable' and to enable the
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output buffer use 'output-enable'.
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To link the pin configurations with UART0 device, use pinctrl-N property in the
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device node, where 'N' is the zero-based state index (0 is the default state).
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Following previous example:
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&uart0 {
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pinctrl-0 = <&uart0_default>;
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pinctrl-names = "default";
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status = "okay";
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};
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If only the required properties are supplied, the pin configuration register
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will be assigned the following values:
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- input and output buffers disabled
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- internal pull not enabled
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- slew rate "fastest"
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- invert disabled
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- drive strength disabled.
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Additionally, following settings are currently not supported and default to
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the values indicated below:
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- Safe Mode Control (disabled)
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- Pad Keeping (disabled)
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- Input Filter (disabled).
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compatible: "nxp,s32k3-pinctrl"
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include: base.yaml
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child-binding:
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description: NXP S32 pin controller pin group.
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child-binding:
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description: NXP S32 pin controller pin configuration node.
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include:
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- name: pincfg-node.yaml
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property-allowlist:
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- bias-disable
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- bias-pull-down
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- bias-pull-up
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- input-enable
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- output-enable
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properties:
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pinmux:
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required: true
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type: array
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description: |
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An array of pins sharing the same group properties. The pins must be
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defined using the S32_PINMUX macros that encodes all the pin muxing
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information in a 32-bit value.
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slew-rate:
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type: string
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enum:
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- "fastest"
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- "slowest"
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default: "fastest"
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description: |
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Slew rate control. Can be either slowest or fastest setting.
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See the SoC reference manual for applicability of this setting.
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nxp,invert:
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type: boolean
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description: |
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Invert the signal selected by Source Signal Selection (SSS) before
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transmitting it to the associated destination (chip pin or module port).
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nxp,drive-strength:
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type: boolean
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description: |
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Drive strength enable.
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See the SoC reference manual for applicability of this setting.
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