70 lines
2.1 KiB
YAML
70 lines
2.1 KiB
YAML
# Copyright 2022, 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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description: |
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MCI IO MUX pin control node. This node defines pin configurations in pin
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groups, and has the 'pinctrl' node identifier in the SOC's devicetree. Each
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group within the pin configuration defines a peripheral's pin configuration.
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Each numbered subgroup represents pins with shared configuration for that
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peripheral. The 'pinmux' property of each group selects the pins to be
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configured with these properties. For example, here is a configuration
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for FLEXCOMM0 pins:
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pinmux_flexcomm0_usart: pinmux_flexcomm0_usart {
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group0 {
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pinmux = <IO_MUX_FC0_USART_DATA_IO2>,
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<IO_MUX_FC0_USART_DATA_IO3>;
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slew-rate = "normal";
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};
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};
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If only the required properties are supplied, the pin will be configured
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as normal drive strength and no pull. This corresponds to the following
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pin settings:
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PAD_PU_PD_ENx = (0x0 << pin_index)
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SR_CONFIGx = (0x2 << pin_index)
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Note
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Note the inherited pinctrl properties defined below have the following effects:
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bias-pull-up: PAD_PU_PD_ENx= (0x1 << pin_index)
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bias-pull-down: PAD_PU_PD_ENx= (0x10 << pin_index)
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compatible: "nxp,mci-io-mux"
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include:
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- name: base.yaml
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child-binding:
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description: MCI IO MUX pin controller pin group
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child-binding:
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description: |
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MCI IO MUX pin controller pin configuration node
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include:
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- name: pincfg-node.yaml
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property-allowlist:
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- bias-pull-up
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- bias-pull-down
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properties:
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pinmux:
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required: true
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type: array
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description: |
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Pin mux selection for this group. See the SOC level pinctrl header
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file in NXP's HAL for a defined list of these options.
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slew-rate:
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required: true
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type: string
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enum:
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- "slow"
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- "normal"
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- "fast"
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- "ultra"
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description: |
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Pin output slew rate. Sets the GPIOxx_SR field in the SR_CONFIGx
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register.
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0 - slow slew rate
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1 - normal slew rate
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2 - fast slew rate
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3 - fastest slew rate (ultra)
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