123 lines
3.7 KiB
YAML
123 lines
3.7 KiB
YAML
# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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# an affiliate of Cypress Semiconductor Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Infineon CAT1 Pinctrl container node
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This is a singleton node responsible for controlling the pin function selection
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and pin properties. For example, you can use this node to route
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UART0 RX to a particular port/pin and enable the pull-up resistor on that
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pin.
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The node has the 'pinctrl' node label set in SoC's devicetree,
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so you can modify it like this:
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&pinctrl {
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/* Your modifications go here */
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};
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Pin configuration can also specify the pin properties, for example the
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'bias-pull-up' property. Here is a list of the supported standard pin
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properties:
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* bias-high-impedance
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* bias-pull-up
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* bias-pull-down
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* drive-open-drain
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* drive-open-source
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* drive-push-pull (strong)
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* input-enable (input-buffer)
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Infineon CAT1 SoC's devicetree includes a set of pre-defined pin control
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Nodes, which can be found via MPN dtsi.
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For example, board cy8cproto_062_4343w uses the CY8C624ABZI_S2D44 part, so
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board dts (boards\arm\cy8cproto_062_4343w\cy8cproto_062_4343w.dts) includes MPN dts
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(infineon/psoc6/mpns/CY8C624ABZI_S2D44.dtsi).
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Each MPN dtsi includes package dtsi (../psoc6_xx/psoc6_xx.yyy-zzz.dtsi),
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For example, CY8C624ABZI_S2D44 includes "../psoc6_02/psoc6_02.124-bga.dtsi".
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An example of pre-defined pin control from package dtsi (e.g. psoc6_02.124-bga.dtsi):
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p3_0_scb2_uart_rx - RX pin UART2 (SCB2) which connected to port3.0
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/omit-if-no-ref/ p3_0_scb2_uart_rx: p3_0_scb2_uart_rx {
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pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_6)>;
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};
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Refer to psoc6_02.124-bga.dtsi for the list of all pre-defined pin control nodes.
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NOTE1 Pre-defined pin control nodes use macro DT_CAT1_PINMUX to
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initialize pinmux. DT_CAT1_PINMUX has the following input parameters
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DT_CAT1_PINMUX(port_number, pin_number, hsiom),
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hsiom is defined in the HSIOM_SEL_xxx macros in the
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zephyr\include\zephyr\dt-bindings\pinctrl\ifx_cat1-pinctrl.h file.
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You can use DT_CAT1_PINMUX to define your own pin control node:
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&pinctrl {
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my_uart_rx: my_uart_rx {
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pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_6)>;
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};
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};
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NOTE2 Pre-defined pin control nodes do not have bias pin configuration.
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The bias configuration can be updated in board-pinctrl.dtsi
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&pinctrl {
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/* Configure pin control Bias mode for uart2 pins */
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p3_1_scb2_uart_tx {
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drive-push-pull;
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};
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p3_0_scb2_uart_rx {
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input-enable;
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};
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p3_2_scb2_uart_rts {
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drive-push-pull;
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};
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p3_3_scb2_uart_cts {
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input-enable;
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};
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};
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An example of the usage of pre-defined pin control nodes in your board's DTS file:
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&uart5 {
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pinctrl-0 = <&p5_1_scb5_uart_tx &p5_0_scb5_uart_rx>;
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pinctrl-names = "default";
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};
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/* Configure pin control bias mode for uart5 pins */
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&p5_1_scb5_uart_tx {
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drive-push-pull;
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};
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&p5_0_scb5_uart_rx {
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input-enable;
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};
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compatible: "infineon,cat1-pinctrl"
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include: base.yaml
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child-binding:
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description: This binding gives a base representation of the Infineon CAT1 pins configuration
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include:
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- name: pincfg-node.yaml
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property-allowlist:
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- bias-high-impedance
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- bias-pull-down
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- bias-pull-up
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- drive-push-pull
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- drive-open-drain
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- drive-open-source
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- input-enable
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properties:
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pinmux:
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description: |
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Encodes port/pin and alternate function.
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required: true
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type: int
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