137 lines
5.3 KiB
YAML
137 lines
5.3 KiB
YAML
# Copyright (c) 2021 Teslabs Engineering S.L.
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# SPDX-License-Identifier: Apache-2.0
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description: |
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The GD32 pin controller (AFIO model) is a singleton node responsible for
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controlling pin function selection and pin properties. For example, you can
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use this node to route USART0 RX to pin PA10 and enable the pull-up resistor
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on the pin. Remapping is also supported.
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The node has the 'pinctrl' node label set in your SoC's devicetree,
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so you can modify it like this:
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&pinctrl {
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/* your modifications go here */
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};
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All device pin configurations should be placed in child nodes of the
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'pinctrl' node, as shown in this example:
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/* You can put this in places like a board-pinctrl.dtsi file in
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* your board directory, or a devicetree overlay in your application.
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*/
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/* include pre-defined combinations for the SoC variant used by the board */
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#include <dt-bindings/pinctrl/gd32f403z(k-i-g-e-c-b)xx-pinctrl.h>
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&pinctrl {
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/* configuration for the usart0 "default" state */
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usart0_default: usart0_default {
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/* group 1 */
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group1 {
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/* configure PA9 as USART0 TX and PA11 as USART0 CTS (no remap) */
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pinmux = <USART0_TX_PA9_NORMP>, <USART0_CTS_PA11_NORMP>;
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};
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/* group 2 */
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group2 {
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/* configure PA10 as USART0 RX and PA12 as USART0 RTS (no remap) */
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pinmux = <USART0_RX_PA10_NORMP>, <USART0_RTS_PA12_NORMP>;
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/* both PA10 and PA12 have pull-up enabled */
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bias-pull-up;
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};
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/* configuration for the usart0 "sleep" state */
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usart0_sleep: usart0_sleep {
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/* group 1 */
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group1 {
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/* configure PA9, PA10, PA11 and PA12 in analog mode */
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pinmux = <ANALOG_PA9>, <ANALOG_PA10>, <ANALOG_PA12>, <ANALOG_PA11>;
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};
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};
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The 'usart0_default' child node encodes the pin configurations for a
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particular state of a device; in this case, the default (that is, active)
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state. Similarly, 'usart0_sleep' child node encodes the pin configurations
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for the sleep state (used in device low power mode). Note that analog mode
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is used for low power states because it disconnects the pin pull-up/down
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resistor, schmitt trigger, and output buffer.
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As shown, pin configurations are organized in groups within each child node.
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Each group can specify a list of pin function selections in the 'pinmux'
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property.
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A group can also specify shared pin properties common to all the specified
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pins, such as the 'bias-pull-up' property in group 2. Here is a list of
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supported standard pin properties:
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- drive-push-pull: Push-pull drive mode (default, not required). Only
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applies for GPIO_IN mode.
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- drive-open-drain: Open-drain drive mode. Only applies for GPIO_IN mode.
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- bias-disable: Disable pull-up/down (default, not required). Only applies
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for GPIO_IN mode.
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- bias-pull-up: Enable pull-up resistor. Only applies for GPIO_IN mode.
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- bias-pull-down: Enable pull-down resistor. Only applies for GPIO_IN mode.
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- slew-rate: Set the maximum speed (and so the slew-rate) of the output
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signal (default: 2MHz). Only applies for ALTERNATE mode.
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Note that drive and bias options are mutually exclusive.
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Peripherals that are remappable will have their pre-defined macros suffixed
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with the remap option being selected, for example:
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- CAN0_RX_PA11_NORMP: No remap
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- CAN0_RX_PB8_PRMP: Partial remap
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- CAN0_RX_PD0_FRMP: Full remap
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It is important that **ALL** pinmux entries share the same remap. For
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example:
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&pinctrl {
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can0_default: can0_default {
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group1 {
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pinmux = <CAN0_RX_PD0_FRMP>, <CAN0_TX_PD1_FRMP>;
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/* ^^^^ ^^^^ */
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/* CAN0 pins are remapped choosing the full remap option */
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};
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};
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};
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To link pin configurations with a device, use a pinctrl-N property for some
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number N, like this example you could place in your board's DTS file:
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#include "board-pinctrl.dtsi"
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&usart0 {
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pinctrl-0 = <&usart0_default>;
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pinctrl-1 = <&usart0_sleep>;
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pinctrl-names = "default", "sleep";
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};
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compatible: "gd,gd32-pinctrl-afio"
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include: gd,gd32-pinctrl-common.yaml
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child-binding:
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description: |
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Each child node defines the configuration for a particular state.
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child-binding:
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description: |
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The grandchild nodes group pins that share the same pin configuration.
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properties:
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slew-rate:
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type: string
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default: "max-speed-2mhz"
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enum:
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- "max-speed-10mhz"
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- "max-speed-2mhz"
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- "max-speed-50mhz"
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- "max-speed-highest"
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description: |
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Set the maximum speed of a pin. This setting effectively limits the
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slew rate of the output signal. Defaults to "max-speed-2mhz", the SoC
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default. The max-speed-highest option may not be available on all SoC
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variants. If selected and not available the 50 MHz maximum speed will
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be used instead. Note that usage of max-speed-highest may require
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enabling the I/O compensation cell (refer to the gd,gd32-afio binding
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for more details).
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