99 lines
3.2 KiB
YAML
99 lines
3.2 KiB
YAML
# Copyright (c) 2023 Jeroen van Dooren <jeroen.van.dooren@nobleo.nl>
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# SPDX-License-Identifier: Apache-2.0
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description: |
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STM32 BDMA controller
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The STM32 BDMA is a general-purpose direct memory access controller
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capable of supporting 5 or 6 or 7 or 8 independent BDMA channels.
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Each channel can have up to 8 requests.
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BDMA clients connected to the STM32 BDMA controller must use the format
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described in the dma.txt file, using a four-cell specifier for each
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channel: a phandle to the BDMA controller plus the following four integer cells:
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1. channel: the bdma stream from 0 to <bdma-requests>
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2. slot: bdma request
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3. channel-config: A 32bit mask specifying the BDMA channel configuration
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which is device dependent:
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-bit 6-7 : Direction (see dma.h)
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0x0: MEM to MEM
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0x1: MEM to PERIPH
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0x2: PERIPH to MEM
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0x3: reserved for PERIPH to PERIPH
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-bit 9 : Peripheral Increment Address
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0x0: no address increment between transfers
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0x1: increment address between transfers
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-bit 10 : Memory Increment Address
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0x0: no address increment between transfers
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0x1: increment address between transfers
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-bit 11-12 : Peripheral data size
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0x0: Byte (8 bits)
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0x1: Half-word (16 bits)
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0x2: Word (32 bits)
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0x3: reserved
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-bit 13-14 : Memory data size
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0x0: Byte (8 bits)
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0x1: Half-word (16 bits)
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0x2: Word (32 bits)
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0x3: reserved
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-bit 15: Peripheral Increment Offset Size
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0x0: offset size is linked to the peripheral bus width
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0x1: offset size is fixed to 4 (32-bit alignment)
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-bit 16-17 : Priority level
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0x0: low
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0x1: medium
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0x2: high
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0x3: very high
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examples for stm32h7
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bdma1: dma-controller@58025400 {
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compatible = "st,stm32-bdma";
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...
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st,mem2mem;
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dma-requests = <7>;
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status = "disabled";
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};
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For the client part, example for STM32H743 on BDMA1 instance
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using dmamux2
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&adc3 {
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dmas = < &dmamux2 0 17 0x2C80 >;
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dma-names = "dmamux";
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};
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compatible: "st,stm32-bdma"
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include: dma-controller.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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st,mem2mem:
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type: boolean
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description: If the BDMA controller supports memory to memory transfer
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dma-offset:
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type: int
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description: >
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offset in the table of channels when mapping to a DMAMUX
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for 1st dma instance, offset is 0,
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for 2nd dma instance, offset is the nb of dma channels of the 1st dma,
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for 3rd dma instance, offset is the nb of dma channels of the 2nd dma
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plus the nb of dma channels of the 1st dma instance, etc.
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"#dma-cells":
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const: 4
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# Parameter syntax of stm32 follows the dma client dts syntax
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# in the Linux kernel declared in
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# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/st,stm32-dma.yaml
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dma-cells:
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- channel
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- slot
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- channel-config
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