100 lines
3.4 KiB
YAML
100 lines
3.4 KiB
YAML
# Copyright (c) 2022, TOKITA Hiroshi <tokita.hiroshi@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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description: |
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GD32 DMA controller with FIFO
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channel: Select channel for data transmitting
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slot: Select peripheral to connect DMA
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config: A 32bit mask specifying the DMA channel configuration
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- bit 6-7: Direction (see dma.h)
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- 0x0: MEMORY to MEMORY
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- 0x1: MEMORY to PERIPH
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- 0x2: PERIPH to MEMORY
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- 0x3: reserved for PERIPH to PERIPH
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- bit 9: Peripheral address increase
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- 0x0: no address increment between transfers
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- 0x1: increment address between transfers
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- bit 10: Memory address increase
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- 0x0: no address increase between transfers
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- 0x1: increase address between transfers
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- bit 11-12: Peripheral data width
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- 0x0: 8 bits
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- 0x1: 16 bits
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- 0x2: 32 bits
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- 0x3: reserved
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- bit 13-14: Memory data width
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- 0x0: 8 bits
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- 0x1: 16 bits
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- 0x2: 32 bits
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- 0x3: reserved
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- bit 15: Peripheral Increment Offset Size
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- 0x0: offset size is linked to the peripheral bus width
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- 0x1: offset size is fixed to 4 (32-bit alignment)
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- bit 16-17: Priority
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- 0x0: low
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- 0x1: medium
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- 0x2: high
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- 0x3: very high
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fifo-threshold: A 32bit bitfield value specifying FIFO threshold
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- bit 0-1: Depth of DMA's FIFO used by burst-transfer.
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- 0x0: 1 word
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- 0x1: 2 word
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- 0x2: 3 word
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- 0x3: 4 word
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Example of devicetree configuration
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&spi0 {
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status = "okay";
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pinctrl-0 = <&spi0_default>;
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pinctrl-names = "default";
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cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
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dmas = <&dma1 0 3 0 0>, <&dma1 5 3 GD32_DMA_PRIORITY_HIGH 0>
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dma-names = "rx", "tx";
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};
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"spi0" uses dma1 for transmitting and receiving in the example.
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Each is named "rx" and "tx".
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The first cell assigns channel 0 to receive and channel 5 to transmit.
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The second cell is slot. Both channels select 3.
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What the slot number '3' means depends on the DMA controller and channel.
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See the Hardware manual.
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The config that places on the third can take various configs.
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But the setting used depends on each driver implementation.
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Set the priority for the transmitting channel as HIGH, LOW(the default) for receive channel.
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The fifo-threshold cell that places the fourth is configuring FIFO threshold.
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The behavior of burst transfer determines by data-width in the config cell,
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burst-length in the dma_config struct, and fifo-threshold.
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A single burst transfer transfers [(4 * fifo-threshold)] bytes using with DMA's FIFO.
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Where (data-width * burst-length) must be multiple numbers of burst transfer size.
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For example, In the case of data-width is 'byte' and burst-length is 8.
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If the fifo-threshold is a 2-word case, it runs one burst transfer to transfer 8 bytes.
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Or the fifo-threshold is a 4-word case, runs two times burst transfer to transferring 8 bytes each
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time.
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compatible: "gd,gd32-dma-v1"
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include: ["reset-device.yaml", "gd,gd32-dma-base.yaml"]
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properties:
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"#dma-cells":
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const: 4
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dma-cells:
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- channel
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- slot
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- config
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- fifo-threshold
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