140 lines
3.5 KiB
YAML
140 lines
3.5 KiB
YAML
# Copyright (c) 2023, STMicroelectronics
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# SPDX-License-Identifier: Apache-2.0
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description: |
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STM32 Reset and Clock controller node.
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This node is in charge of system clock ('SYSCLK') source selection and controlling
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clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.
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Configuring STM32 Reset and Clock controller node:
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System clock source should be selected amongst the clock nodes available in "clocks"
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node (typically 'clk_hse, clk_hsi', 'pll').
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Core clock frequency should also be defined, using "clock-frequency" property.
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Note:
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Core clock frequency = SYSCLK / AHB prescaler
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Last, peripheral bus clocks (typically PCLK1, PCLK2, PCLK7) should be configured using
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matching prescaler properties.
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Here is an example of correctly configured rcc node:
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&rcc {
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clocks = <&pll>; /* Select pll as SYSCLK source */
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ahb-prescaler = <2>;
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clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
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apb1-presacler = <1>;
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apb2-presacler = <1>;
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apb7-presacler = <7>;
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}
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Specifying a gated clock:
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To specify a gated clock, a peripheral should define a "clocks" property encoded
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in the following way:
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... {
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...
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
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...
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}
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After the phandle referring to rcc node, the first index specifies the registers of
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the bus controlling the peripheral and the second index specifies the bit used to
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control the peripheral clock in that bus register.
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Specifying an alternate clock source:
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Specifying an alternate source clock could be done by adding a clock specifier to the
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clock property:
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... {
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...
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>,
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<&rcc STM32_SRC_HSI I2C1_SEL(2)>;
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...
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}
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In this example I2C1 device is assigned HSI as clock source.
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It is device driver's responsibility to query and use clock source information in
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accordance with clock_control API specifications.
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compatible: "st,stm32wba-rcc"
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include: [clock-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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"#clock-cells":
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const: 2
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clock-frequency:
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required: true
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type: int
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description: |
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default frequency in Hz for clock output (HCLK1)
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ahb-prescaler:
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type: int
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required: true
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enum:
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- 1
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- 2
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- 4
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- 8
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- 16
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description: |
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Common AHB1, AHB2, AHB4 prescaler. Defines actual core clock frequency
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(HCLK) based on system frequency input. AKA HPRE.
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The HCLK clocks CPU, AHB1, AHB2, memories and DMA.
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ahb5-prescaler:
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type: int
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enum:
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- 1
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- 2
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- 3
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- 4
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- 6
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description: |
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AHB5 prescaler. Defines actual core clock frequency (HCLK5) based on
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system frequency input. It is used to limit HCLK5 below 32MHz.
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Only required when SysClock source is PLL1.
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AKA HPRE5.
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apb1-prescaler:
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type: int
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required: true
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enum:
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- 1
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- 2
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- 4
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- 8
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- 16
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apb2-prescaler:
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type: int
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required: true
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enum:
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- 1
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- 2
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- 4
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- 8
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- 16
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apb7-prescaler:
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type: int
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required: true
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enum:
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- 1
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- 2
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- 4
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- 8
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- 16
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ahb5-div:
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type: boolean
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description: |
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AHB5 divider. Applies only when SysClock source is HSI16 or HSE32.
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When enabled, AHB5 clock is SysClock / 2.
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When disabled, SysClock is not divided.
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clock-cells:
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- bus
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- bits
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