79 lines
1.7 KiB
YAML
79 lines
1.7 KiB
YAML
# Copyright (c) 2021, Linaro ltd
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# SPDX-License-Identifier: Apache-2.0
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description: |
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PLL node binding for STM32L4 and STM32L5 devices
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It can be used to describe 3 different PLLs: PLL, PLLSAI1 and PLLSAI2.
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Only main PLL is supported for now.
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These PLLs could take one of clk_hse, clk_hsi or clk_msi as input clock, with
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an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
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clock in this acceptable range.
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Each PLL can have up to 3 output clocks and for each output clock, the
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frequency can be computed with the following formulae:
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f(PLL_P) = f(VCO clock) / PLLP --> PLLSAI3CLK
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f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48M1CLK
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f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
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with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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The PLL output frequency must not exceed 80 MHz.
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compatible: "st,stm32l4-pll-clock"
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include: [clock-controller.yaml, base.yaml]
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properties:
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"#clock-cells":
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const: 0
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clocks:
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required: true
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div-m:
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type: int
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required: true
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description: |
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Division factor for the main PLL and audio PLLs (PLLSAI1 and PLLSAI2)
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input clock
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Valid range: 1 - 8
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mul-n:
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type: int
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required: true
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description: |
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Main PLL multiplication factor for VCO
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Valid range: 8 - 86
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div-p:
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type: int
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description: |
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Main PLL division factor for PLLSAI3CLK
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enum:
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- 7
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- 17
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div-q:
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type: int
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description: |
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Main PLL division factor for PLL48M1CLK (48 MHz clock).
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enum:
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- 2
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- 4
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- 6
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- 8
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div-r:
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type: int
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required: true
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description: |
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Main PLL division factor for PLLCLK (system clock)
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enum:
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- 2
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- 4
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- 6
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- 8
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