60 lines
1.3 KiB
YAML
60 lines
1.3 KiB
YAML
# Copyright (c) 2021, Linaro ltd
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# SPDX-License-Identifier: Apache-2.0
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description: |
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STM32L0 and STM32L1 Main PLL node binding:
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Takes one of clk_hse, clk_hsi or clk_msi as input clock, with an
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input frequency from 2 to 24 MHz.
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The desired PLL frequency can be computed with the following formula:
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f(PLL) = f(VCO clock) / PLLDIV --> PLLCLK (System Clock)
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with f(VCO clock) = f(PLL clock input) × PLLMUL --> PLLVCO
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The PLL output frequency must not exceed 32 MHz.
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compatible: "st,stm32l0-pll-clock"
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include: [clock-controller.yaml, base.yaml]
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properties:
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"#clock-cells":
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const: 0
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clocks:
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required: true
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div:
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type: int
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required: true
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description: |
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PLL output division
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enum:
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- 2
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- 3
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- 4
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mul:
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type: int
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required: true
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description: |
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PLL multiplication factor for VCO
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The PLL VCO clock frequency must not exceed:
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- 96 MHz when the product is in Range 1
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- 48 MHz when the product is in Range 2
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- 24 MHz when the product is in Range 3
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If the USB uses the PLL as clock source, the PLL VCO clock must be
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programmed to output a 96 MHz frequency (USBCLK = PLLVCO/2).
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enum:
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- 3
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- 4
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- 6
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- 8
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- 12
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- 16
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- 24
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- 32
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- 48
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