42 lines
1.2 KiB
YAML
42 lines
1.2 KiB
YAML
# Copyright (c) 2021, Linaro ltd
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Main PLL node binding for STM32F0 and STM32F3 devices.
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Takes one of clk_hse or clk_hsi as input clock.
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Note: Some STM32F0 SoC variants (STM32072 for instance) may also support HSI48
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as input clock. This case is not supported yet.
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Frequency calculation for output clock is as follows:
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f(PLLCLK) = f(PLLIN) x PLLMUL --> SYSCLK (System Clock)
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with, depending on the case:
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If input_clk = clk_hse
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f(PLLIN) = f(input_clk) / PREDIV
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If input_clk = clk_hsi
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On STM32F3, STM32F03x, STM32F05x, STM32F030x4, STM32F030x6 and STM32F030x8
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f(PLLIN) = f(input_clk) / 2
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On STM32F04x, STM32F07x, STM32F09x, STM32F070x6, STM32F070xB and STM32F030xC
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f(PLLIN) = f(input_clk) / PREDIV
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The PLL output frequency must be set in range 16-48MHz
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compatible: "st,stm32f0-pll-clock"
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include:
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- name: st,stm32f105-pll-clock.yaml
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property-blocklist:
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- mul
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- otgfspre
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properties:
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mul:
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type: int
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required: true
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description: |
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PLL multiplication factor for output clock
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Valid range: 2 - 16
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