137 lines
4.2 KiB
YAML
137 lines
4.2 KiB
YAML
# Copyright (c) 2021, Linaro ltd
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# SPDX-License-Identifier: Apache-2.0
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description: |
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STM32 Reset and Clock controller node.
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This node is in charge of system clock ('SYSCLK') source selection and controlling
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clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.
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Configuring STM32 Reset and Clock controller node:
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System clock source should be selected amongst the clock nodes available in "clocks"
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node (typically 'clk_hse, clk_hsi', 'pll', ...).
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Core clock frequency should also be defined, using "clock-frequency" property.
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Note:
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Core clock frequency = SYSCLK / AHB prescaler
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Last, peripheral bus clocks (typically PCLK1, PCLK2) should be configured using matching
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prescaler properties.
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Here is an example of correctly configured rcc node:
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&rcc {
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clocks = <&pll>; /* Select 80MHz pll as SYSCLK source */
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ahb-prescaler = <2>;
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clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
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apb1-presacler = <1>;
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apb2-presacler = <1>;
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}
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Specifying a gated clock:
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To specify a gated clock, a peripheral should define a "clocks" property encoded
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in the following way:
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... {
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...
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
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...
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}
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After the phandle referring to rcc node, the first index specifies the registers of
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the bus controlling the peripheral and the second index specifies the bit used to
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control the peripheral clock in that bus register.
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The gated clock is required when accessing to the peripheral controller is needed
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(generally for configuring the device). If dual clock domain is not used, it is
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also used for peripheral operation.
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Specifying a domain clock source:
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Specifying a domain source clock could be done by adding a clock specifier to the
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clock property:
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... {
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...
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>,
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<&rcc STM32_SRC_HSI I2C1_SEL(2)>;
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...
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}
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In this example, I2C1 device is assigned HSI as domain clock source.
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Domain clock is independent from the bus/gated clock and allows access to the device's
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register while the gated clock is off. As it doesn't feed the peripheral's controller, it
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allows peripheral operation, but can't be used for peripheral configuration.
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It is peripheral driver's responsibility to query and use clock source information in
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accordance with clock_control API specifications.
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Since the peripheral subsystem rate is dictated by the clock used for peripheral
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operation, same clock should be used in calls to `clock_control_get_rate()`
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Note 1: No additional specifier means gating clock is also the clock source (ie
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'PCLK/PCLK1/PCLK2' depending on the device). There is no need to add a second
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cell to explicitly set it.
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Note 2: Default peripheral clock configuration (ie the one provided in *.dsti files)
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should be the one matching SoC reset state. Confere reference manual to check
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what is the reset value of the clock source for each peripheral.
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compatible: "st,stm32-rcc"
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include: [clock-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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"#clock-cells":
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const: 2
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clock-frequency:
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required: true
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type: int
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description: |
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default frequency in Hz for clock output
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ahb-prescaler:
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type: int
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required: true
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enum:
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- 1
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- 2
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- 4
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- 8
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- 16
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- 64
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- 128
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- 256
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- 512
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description: |
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AHB prescaler. Defines actual core clock frequency (HCLK)
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based on system frequency input.
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The HCLK clocks CPU, AHB, memories and DMA.
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apb1-prescaler:
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type: int
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required: true
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enum:
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- 1
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- 2
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- 4
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- 8
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- 16
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apb2-prescaler:
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type: int
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required: true
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enum:
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- 1
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- 2
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- 4
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- 8
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- 16
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undershoot-prevention:
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type: boolean
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description: |
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On some parts, it could be required to set up highest core frequencies
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(>80MHz) in two steps in order to prevent undershoot.
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This is done by applying an intermediate AHB prescaler before switching
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System Clock source to PLL. Once done, prescaler is set back to expected
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value.
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clock-cells:
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- bus
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- bits
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