223 lines
6.1 KiB
YAML
223 lines
6.1 KiB
YAML
# Copyright (c) 2024 Nuvoton Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Nuvoton, NPCM PCC (Power and Clock Controller) node.
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Besides power management, this node is also in charge of configuring the
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Oscillator Frequency Multiplier Clock (OFMCLK), which is derived from
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High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
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and most of NPCM hardware modules.
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Here is an example of configuring OFMCLK and the other clock sources derived
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from it in board dts file.
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&pcc {
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clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
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core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
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apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
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apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
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apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
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apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
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fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
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i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
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};
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compatible: "nuvoton,npcm-pcc"
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include: [clock-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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clock-frequency:
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required: true
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type: int
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description: |
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Default frequency in Hz for HFCG output clock (OFMCLK). Currently,
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only the following values are allowed:
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100000000, 100 MHz
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96000000, 96 MHz
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80000000, 80 MHz
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66000000, 66 MHz
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50000000, 50 MHz
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48000000, 48 MHz
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40000000, 40 MHz
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33000000, 33 MHz
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enum:
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- 100000000
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- 96000000
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- 80000000
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- 66000000
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- 50000000
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- 48000000
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- 40000000
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- 33000000
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core-prescaler:
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type: int
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required: true
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description: |
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Core clock prescaler (FPRED). It sets the Core frequency, CORE_CLK, by
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dividing OFMCLK(MCLK) and needs to meet the following requirements.
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- The maximum CLK frequency is either the MCLK frequency divided by 1 or 100 MHz.
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- Only the following values are allowed:
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1, CORE_CLK = OFMCLK
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2, CORE_CLK = OFMCLK / 2
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3, CORE_CLK = OFMCLK / 3
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4, CORE_CLK = OFMCLK / 4
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5, CORE_CLK = OFMCLK / 5
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6, CORE_CLK = OFMCLK / 6
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7, CORE_CLK = OFMCLK / 7
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8, CORE_CLK = OFMCLK / 8
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9, CORE_CLK = OFMCLK / 9
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10, CORE_CLK = OFMCLK / 10
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enum:
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- 1
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- 2
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- 3
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- 4
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- 5
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- 6
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- 7
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- 8
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- 9
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- 10
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apb1-prescaler:
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type: int
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required: true
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description: |
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APB1 prescaler. It sets the APB1 bus frequency, APB1_CLK, by dividing
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OFMCLK(MCLK) and needs to meet the following requirements.
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- The maximum APB1_CLK frequency is either the MCLK frequency divided by 1 or 100 MHz.
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- Only the following values are allowed:
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1, APB1_CLK = OFMCLK
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2, APB1_CLK = OFMCLK / 2
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3, APB1_CLK = OFMCLK / 3
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4, APB1_CLK = OFMCLK / 4
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5, APB1_CLK = OFMCLK / 5
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6, APB1_CLK = OFMCLK / 6
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7, APB1_CLK = OFMCLK / 7
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8, APB1_CLK = OFMCLK / 8
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9, APB1_CLK = OFMCLK / 9
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10, APB1_CLK = OFMCLK / 10
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enum:
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- 1
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- 2
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- 3
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- 4
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- 5
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- 6
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- 7
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- 8
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- 9
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- 10
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apb2-prescaler:
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type: int
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required: true
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description: |
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APB2 prescaler. It sets the APB2 bus frequency, APB2_CLK, by dividing
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OFMCLK(MCLK) and needs to meet the following requirements.
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- The maximum APB2_CLK frequency is either the MCLK frequency divided by 1 or 100 MHz.
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- Only the following values are allowed:
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1, APB2_CLK = OFMCLK
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2, APB2_CLK = OFMCLK / 2
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3, APB2_CLK = OFMCLK / 3
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4, APB2_CLK = OFMCLK / 4
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5, APB2_CLK = OFMCLK / 5
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6, APB2_CLK = OFMCLK / 6
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7, APB2_CLK = OFMCLK / 7
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8, APB2_CLK = OFMCLK / 8
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9, APB2_CLK = OFMCLK / 9
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10, APB2_CLK = OFMCLK / 10
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enum:
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- 1
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- 2
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- 3
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- 4
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- 5
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- 6
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- 7
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- 8
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- 9
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- 10
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apb3-prescaler:
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type: int
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required: true
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description: |
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APB3 prescaler. It sets the APB3 bus frequency, APB3_CLK, by dividing
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OFMCLK(MCLK) and needs to meet the following requirements.
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- The maximum APB3_CLK frequency is either the MCLK frequency divided by 1 or 100 MHz.
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- Only the following values are allowed:
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1, APB3_CLK = OFMCLK
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2, APB3_CLK = OFMCLK / 2
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3, APB3_CLK = OFMCLK / 3
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4, APB3_CLK = OFMCLK / 4
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5, APB3_CLK = OFMCLK / 5
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6, APB3_CLK = OFMCLK / 6
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7, APB3_CLK = OFMCLK / 7
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8, APB3_CLK = OFMCLK / 8
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9, APB3_CLK = OFMCLK / 9
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10, APB3_CLK = OFMCLK / 10
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enum:
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- 1
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- 2
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- 3
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- 4
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- 5
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- 6
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- 7
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- 8
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- 9
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- 10
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ahb6-prescaler:
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type: int
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required: true
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description: |
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AHB6 prescaler. The AHB6 bus clock (AHB6_CLK) is derived from the Core clock (CLK) via a
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programmable divider controlled by the AHB6DIV field in HFCGP register.
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Its frequency must be set according to the following rules:
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- The maximum AHB6_CLK frequency is either the CLK frequency divided by 1 or 100 MHz.
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- Only the following values are allowed:
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1, AHB6_CLK = CORE_CLK
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2, AHB6_CLK = CORE_CLK / 2
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4, AHB6_CLK = CORE_CLK / 4
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enum:
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- 1
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- 2
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- 4
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fiu-prescaler:
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type: int
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required: true
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description: |
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FIU prescaler. The FIU clock (FIUCLK) is derived from the Core clock (CLK) via a
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programmable divider controlled by the FIUDIV field in HFCBCD1 register.
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Its frequency must be set according to the following rules:
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- The maximum FIUCLK frequency is either the CLK frequency divided by 1 or 100MHz.
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- Only the following values are allowed:
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1, FIU_CLK = CORE_CLK
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2, FIU_CLK = CORE_CLK / 2
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4, FIU_CLK = CORE_CLK / 4
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enum:
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- 1
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- 2
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- 4
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i3c-prescaler:
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type: int
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required: true
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description: |
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I3C prescaler. It sets the I3C clk_slow_tc frequency, by dividing
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APB3_CLK and it can be up to 100 MHz.
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enum:
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- 1
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- 2
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- 4
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clock-cells:
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- clk_id
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