155 lines
4.1 KiB
Plaintext
155 lines
4.1 KiB
Plaintext
/*
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* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Derived from DTS extracted with:
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*
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* qemu-system-aarch64 -machine virt -cpu cortex-a53 -nographic
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* -machine dumpdtb=virt.dtb
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*
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* dtc -I dtb -O dts virt.dtb
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*/
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#include <mem.h>
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#include <arm64/armv8-a.dtsi>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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#include <zephyr/dt-bindings/pcie/pcie.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <1>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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};
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uartclk: apb-pclk {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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#clock-cells = <0>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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interrupt-parent = <&gic>;
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gic: interrupt-controller@8000000 {
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compatible = "arm,gic-v3", "arm,gic";
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reg = <0x00 0x8000000 0x00 0x010000>,
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<0x00 0x80a0000 0x00 0xf60000>;
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interrupt-controller;
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#interrupt-cells = <4>;
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status = "okay";
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#size-cells = <0x02>;
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#address-cells = <0x02>;
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its: its@8080000 {
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compatible = "arm,gic-v3-its";
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reg = <0x00 0x8080000 0x00 0x20000>;
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msi-controller;
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};
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};
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uart0: uart@9000000 {
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compatible = "arm,pl011";
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reg = <0x00 0x9000000 0x00 0x1000>;
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status = "disabled";
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL 0>;
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interrupt-names = "irq_0";
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clocks = <&uartclk>;
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};
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flash0: flash@0 {
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compatible = "cfi-flash";
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bank-width = <4>;
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/* As this is pointed to by zephyr,flash we can only handle
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* one value in the reg property, so we comment out the
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* second flash bank for now
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*/
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reg = <0x0 0x0 0x0 DT_SIZE_M(64) /* 0x4000000 DT_SIZE_M(64) */>;
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};
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pcie: pcie@4010000000 {
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compatible = "pci-host-ecam-generic";
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device_type = "pci";
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reg = <0x40 0x10000000 0x00 0x10000000>;
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#size-cells = <0x02>;
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#address-cells = <0x03>;
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ranges = <0x1000000 0x00 0x00 0x00 0x3eff0000 0x00 0x10000
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0x2000000 0x00 0x10000000 0x00 0x10000000 0x00 0x2eff0000
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0x3000000 0x80 0x00 0x80 0x00 0x80 0x00>;
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#interrupt-cells = <0x01>;
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interrupt-map-mask = <0x1800 0x00 0x00 0x07>;
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interrupt-map = <0x00 0x00 0x00 1 &gic 0 0 GIC_SPI
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0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
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0x00 0x00 0x00 2 &gic 0 0 GIC_SPI
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0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
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0x00 0x00 0x00 3 &gic 0 0 GIC_SPI
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0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
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0x00 0x00 0x00 4 &gic 0 0 GIC_SPI
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0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
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0x800 0x00 0x00 1 &gic 0 0 GIC_SPI
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0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
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0x800 0x00 0x00 2 &gic 0 0 GIC_SPI
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0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
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0x800 0x00 0x00 3 &gic 0 0 GIC_SPI
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0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
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0x800 0x00 0x00 4 &gic 0 0 GIC_SPI
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0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
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0x1000 0x00 0x00 1 &gic 0 0 GIC_SPI
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0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
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0x1000 0x00 0x00 2 &gic 0 0 GIC_SPI
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0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
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0x1000 0x00 0x00 3 &gic 0 0 GIC_SPI
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0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
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0x1000 0x00 0x00 4 &gic 0 0 GIC_SPI
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0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
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0x1800 0x00 0x00 1 &gic 0 0 GIC_SPI
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0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
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0x1800 0x00 0x00 2 &gic 0 0 GIC_SPI
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0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
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0x1800 0x00 0x00 3 &gic 0 0 GIC_SPI
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0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
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0x1800 0x00 0x00 4 &gic 0 0 GIC_SPI
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0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
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msi-parent = <&its>;
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bus-range = <0x00 0xff>;
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};
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};
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};
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