112 lines
3.3 KiB
C
112 lines
3.3 KiB
C
/*
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* Copyright (c) 2016, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL CORPORATION OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __IDT_H__
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#define __IDT_H__
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#include <stdint.h>
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#include <string.h>
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#include "qm_common.h"
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#include "qm_soc_regs.h"
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#if (QUARK_SE)
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#define IDT_NUM_GATES (68)
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#elif(QUARK_D2000)
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#define IDT_NUM_GATES (52)
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#endif
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#define IDT_SIZE (sizeof(intr_gate_desc_t) * IDT_NUM_GATES)
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typedef struct idtr {
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uint16_t limit;
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uint32_t base;
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} __attribute__((packed)) idtr_t;
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typedef struct intr_gate_desc {
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uint16_t isr_low;
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uint16_t selector; /* Segment selector */
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/* The format of conf is the following:
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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|p |dpl |ss|d |type | unused |
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type: Gate type
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d: size of Gate
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ss: Storage Segment
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dpl: Descriptor Privilege level
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p: Segment present level
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*/
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uint16_t conf;
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uint16_t isr_high;
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} __attribute__((packed)) intr_gate_desc_t;
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extern intr_gate_desc_t __idt_start[];
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/*
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* Setup IDT gate as an interrupt descriptor and assing the ISR entry point
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*/
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static __inline__ void idt_set_intr_gate_desc(uint32_t vector, uint32_t isr)
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{
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intr_gate_desc_t *desc;
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desc = __idt_start + vector;
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desc->isr_low = isr & 0xFFFF;
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desc->selector = 0x08; /* Code segment offset in GDT */
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desc->conf = 0x8E00; /* type: 0b11 (Interrupt)
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d: 1 (32 bits)
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ss: 0
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dpl: 0
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p: 1
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*/
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desc->isr_high = (isr >> 16) & 0xFFFF;
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}
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/*
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* Initialize Interrupt Descriptor Table.
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* The IDT is initialized with null descriptors: any interrupt at this stage
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* will cause a triple fault.
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*/
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static __inline__ void idt_init(void)
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{
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idtr_t idtr;
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memset(__idt_start, 0x00, IDT_SIZE);
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/* Initialize idtr structure */
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idtr.limit = IDT_SIZE - 1;
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idtr.base = (uint32_t)__idt_start;
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/* Load IDTR register */
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__asm__ __volatile__("lidt %0\n\t" ::"m"(idtr));
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}
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#endif /* __IDT_H__ */
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