482 lines
11 KiB
Plaintext
482 lines
11 KiB
Plaintext
/*
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* Copyright (c) 2019 Linaro Ltd.
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* Copyright (c) 2019 Centaur Analytics, Inc
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/clock/stm32l1_clock.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
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#include <zephyr/dt-bindings/dma/stm32_dma.h>
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#include <zephyr/dt-bindings/adc/stm32f4_adc.h>
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#include <zephyr/dt-bindings/reset/stm32l1_reset.h>
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#include <freq.h>
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/ {
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chosen {
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zephyr,flash-controller = &flash;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m3";
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reg = <0>;
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "st,stm32-hse-clock";
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status = "disabled";
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(16)>;
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status = "disabled";
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};
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clk_msi: clk-msi {
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#clock-cells = <0>;
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compatible = "st,stm32l0-msi-clock";
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msi-range = <5>; /* 2.1MHz (reset value) */
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status = "disabled";
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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status = "disabled";
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_K(37)>;
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status = "disabled";
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};
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pll: pll {
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#clock-cells = <0>;
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compatible = "st,stm32l0-pll-clock";
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status = "disabled";
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};
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};
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soc {
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flash: flash-controller@40023c00 {
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compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";
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reg = <0x40023c00 0x400>;
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interrupts = <4 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00008000>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "st,stm32-nv-flash", "soc-nv-flash";
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write-block-size = <4>;
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/* maximum erase time(ms) for a 128B half-page
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*/
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max-erase-time = <4>;
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};
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};
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rcc: rcc@40023800 {
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compatible = "st,stm32-rcc";
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#clock-cells = <2>;
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reg = <0x40023800 0x400>;
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rctl: reset-controller {
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compatible = "st,stm32-rcc-rctl";
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#reset-cells = <1>;
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};
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};
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rtc: rtc@40002800 {
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compatible = "st,stm32-rtc";
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reg = <0x40002800 0x400>;
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interrupts = <41 0>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
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prescaler = <32768>;
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status = "disabled";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
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resets = <&rctl STM32_RESET(APB1, 17U)>;
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interrupts = <38 0>;
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status = "disabled";
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};
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
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resets = <&rctl STM32_RESET(APB1, 18U)>;
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interrupts = <39 0>;
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status = "disabled";
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};
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uart4: serial@40004c00 {
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compatible = "st,stm32-uart";
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reg = <0x40004c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
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resets = <&rctl STM32_RESET(APB1, 19U)>;
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interrupts = <48 0>;
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status = "disabled";
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};
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uart5: serial@40005000 {
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compatible = "st,stm32-uart";
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reg = <0x40005000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
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resets = <&rctl STM32_RESET(APB1, 20U)>;
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interrupts = <49 0>;
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status = "disabled";
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};
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i2c1: i2c@40005400 {
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compatible = "st,stm32-i2c-v1";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
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interrupts = <31 0>, <32 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32-i2c-v1";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
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interrupts = <33 0>, <34 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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spi1: spi@40013000 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
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interrupts = <35 0>;
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status = "disabled";
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};
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spi2: spi@40003800 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
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interrupts = <36 0>;
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status = "disabled";
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};
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usart1: serial@40013800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40013800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
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resets = <&rctl STM32_RESET(APB2, 14U)>;
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interrupts = <37 0>;
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status = "disabled";
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};
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adc1: adc@40012400 {
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compatible = "st,stm32-adc";
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reg = <0x40012400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
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interrupts = <18 0>;
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status = "disabled";
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#io-channel-cells = <1>;
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temp-channel = <16>;
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vref-channel = <17>;
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resolutions = <STM32_ADC_RES(12, 0x00)
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STM32_ADC_RES(10, 0x01)
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STM32_ADC_RES(8, 0x02)
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STM32_ADC_RES(6, 0x03)>;
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sampling-times = <4 9 16 24 48 96 192 384>;
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};
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dac1: dac@40007400 {
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compatible = "st,stm32-dac";
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reg = <0x40007400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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exti: interrupt-controller@40010400 {
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compatible = "st,stm32-exti";
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <1>;
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reg = <0x40010400 0x400>;
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num-lines = <16>;
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interrupts = <6 0>, <7 0>, <8 0>, <9 0>,
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<10 0>, <23 0>, <40 0>;
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interrupt-names = "line0", "line1", "line2", "line3",
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"line4", "line5-9", "line10-15";
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line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
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<4 1>, <5 5>, <10 6>;
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};
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timers2: timers@40000000 {
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compatible = "st,stm32-timers";
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reg = <0x40000000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
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resets = <&rctl STM32_RESET(APB1, 0U)>;
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interrupts = <28 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers3: timers@40000400 {
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compatible = "st,stm32-timers";
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reg = <0x40000400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
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resets = <&rctl STM32_RESET(APB1, 1U)>;
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interrupts = <29 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers4: timers@40000800 {
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compatible = "st,stm32-timers";
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reg = <0x40000800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
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resets = <&rctl STM32_RESET(APB1, 2U)>;
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interrupts = <30 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers9: timers@40010800 {
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compatible = "st,stm32-timers";
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reg = <0x40010800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000004>;
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resets = <&rctl STM32_RESET(APB2, 2U)>;
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interrupts = <25 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers10: timers@40010c00 {
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compatible = "st,stm32-timers";
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reg = <0x40010c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000008>;
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resets = <&rctl STM32_RESET(APB2, 3U)>;
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interrupts = <26 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers11: timers@40011000 {
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compatible = "st,stm32-timers";
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reg = <0x40011000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
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resets = <&rctl STM32_RESET(APB2, 4U)>;
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interrupts = <27 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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pinctrl: pin-controller@40020000 {
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compatible = "st,stm32-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x40020000 0x2000>;
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gpioa: gpio@40020000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40020000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
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};
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gpiob: gpio@40020400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40020400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
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};
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gpioc: gpio@40020800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40020800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000004>;
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};
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gpiod: gpio@40020c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40020c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000008>;
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};
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gpioe: gpio@40021000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40021000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
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};
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gpioh: gpio@40021400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40021400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
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};
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};
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iwdg: watchdog@40003000 {
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compatible = "st,stm32-watchdog";
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reg = <0x40003000 0x400>;
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status = "disabled";
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};
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wwdg: watchdog@40002c00 {
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compatible = "st,stm32-window-watchdog";
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reg = <0x40002C00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
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interrupts = <0 7>;
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status = "disabled";
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};
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eeprom: eeprom@8080000{
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compatible = "st,stm32-eeprom";
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status = "disabled";
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};
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dma1: dma@40026000 {
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compatible = "st,stm32-dma-v2bis";
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#dma-cells = <2>;
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reg = <0x40026000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1000000>;
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interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
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status = "disabled";
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};
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};
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die_temp: dietemp {
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compatible = "st,stm32-temp-cal";
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ts-cal1-addr = <0x1FF800FA>;
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ts-cal2-addr = <0x1FF800FE>;
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ts-cal1-temp = <30>;
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ts-cal2-temp = <110>;
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ts-cal-vrefanalog = <3000>;
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io-channels = <&adc1 16>;
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status = "disabled";
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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