Maureen Helm 8fa5353bd2 soc: riscv32: Use same clock freq for both rv32m1 cores ... Both the ri5cy and zero-riscy cores in the rv32m1 soc use the same source clock, so we don't need to conditionalize SYS_CLOCK_HW_CYCLES_PER_SEC on the ri5cy core. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>		2019-05-06 14:52:17 -05:00
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openisa_rv32m1	soc: riscv32: Use same clock freq for both rv32m1 cores	2019-05-06 14:52:17 -05:00
riscv-privilege	soc/riscv32-fe310: add label for uart1	2019-04-25 09:19:14 -07:00
CMakeLists.txt	license: cleanup: add SPDX Apache-2.0 license identifier	2019-04-07 08:45:22 -04:00