136 lines
4.0 KiB
C
136 lines
4.0 KiB
C
/*
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* Copyright (c) 2017 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <kernel_internal.h>
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u64_t arch_timing_swap_start;
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u64_t arch_timing_swap_end;
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u64_t arch_timing_irq_start;
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u64_t arch_timing_irq_end;
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u64_t arch_timing_tick_start;
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u64_t arch_timing_tick_end;
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u64_t arch_timing_enter_user_mode_end;
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/* location of the time stamps*/
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u32_t arch_timing_value_swap_end;
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u64_t arch_timing_value_swap_common;
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u64_t arch_timing_value_swap_temp;
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#if defined(CONFIG_NRF_RTC_TIMER)
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#include <nrfx.h>
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/* To get current count of timer, first 1 need to be written into
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* Capture Register and Current Count will be copied into corresponding
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* current count register.
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*/
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#define TIMING_INFO_PRE_READ() (NRF_TIMER2->TASKS_CAPTURE[0] = 1)
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#define TIMING_INFO_OS_GET_TIME() (NRF_TIMER2->CC[0])
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#define TIMING_INFO_GET_TIMER_VALUE() (TIMING_INFO_OS_GET_TIME())
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#define SUBTRACT_CLOCK_CYCLES(val) (val)
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#elif defined(CONFIG_SOC_SERIES_MEC1501X)
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#define TIMING_INFO_PRE_READ()
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#define TIMING_INFO_OS_GET_TIME() (B32TMR1_REGS->CNT)
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#define TIMING_INFO_GET_TIMER_VALUE() (TIMING_INFO_OS_GET_TIME())
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#define SUBTRACT_CLOCK_CYCLES(val) (val)
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#elif defined(CONFIG_X86)
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#define TIMING_INFO_PRE_READ()
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#define TIMING_INFO_OS_GET_TIME() (z_tsc_read())
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#define TIMING_INFO_GET_TIMER_VALUE() (TIMING_INFO_OS_GET_TIME())
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#define SUBTRACT_CLOCK_CYCLES(val) (val)
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#elif defined(CONFIG_CPU_CORTEX_M)
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#include <arch/arm/aarch32/cortex_m/cmsis.h>
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#define TIMING_INFO_PRE_READ()
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#define TIMING_INFO_OS_GET_TIME() (k_cycle_get_32())
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#define TIMING_INFO_GET_TIMER_VALUE() (SysTick->VAL)
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#define SUBTRACT_CLOCK_CYCLES(val) (SysTick->LOAD - (u32_t)val)
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#elif defined(CONFIG_ARC)
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#define TIMING_INFO_PRE_READ()
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#define TIMING_INFO_OS_GET_TIME() (k_cycle_get_32())
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#define TIMING_INFO_GET_TIMER_VALUE() (z_arc_v2_aux_reg_read(_ARC_V2_TMR0_COUNT))
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#define SUBTRACT_CLOCK_CYCLES(val) ((u32_t)val)
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#elif defined(CONFIG_NIOS2)
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#include "altera_avalon_timer_regs.h"
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#define TIMING_INFO_PRE_READ() \
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(IOWR_ALTERA_AVALON_TIMER_SNAPL(TIMER_0_BASE, 10))
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#define TIMING_INFO_OS_GET_TIME() (SUBTRACT_CLOCK_CYCLES(\
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((u32_t)IORD_ALTERA_AVALON_TIMER_SNAPH(TIMER_0_BASE) << 16)\
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| ((u32_t)IORD_ALTERA_AVALON_TIMER_SNAPL(TIMER_0_BASE))))
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#define TIMING_INFO_GET_TIMER_VALUE() (\
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((u32_t)IORD_ALTERA_AVALON_TIMER_SNAPH(TIMER_0_BASE) << 16)\
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| ((u32_t)IORD_ALTERA_AVALON_TIMER_SNAPL(TIMER_0_BASE)))
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#define SUBTRACT_CLOCK_CYCLES(val) \
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((IORD_ALTERA_AVALON_TIMER_PERIODH(TIMER_0_BASE) \
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<< 16 | \
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(IORD_ALTERA_AVALON_TIMER_PERIODL(TIMER_0_BASE))) \
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- ((u32_t)val))
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#else
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#define TIMING_INFO_PRE_READ()
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#define TIMING_INFO_OS_GET_TIME() (k_cycle_get_32())
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#define TIMING_INFO_GET_TIMER_VALUE() (k_cycle_get_32())
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#define SUBTRACT_CLOCK_CYCLES(val) ((u32_t)val)
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#endif /* CONFIG_NRF_RTC_TIMER */
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void read_timer_start_of_swap(void)
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{
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if (arch_timing_value_swap_end == 1U) {
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TIMING_INFO_PRE_READ();
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arch_timing_swap_start = (u32_t) TIMING_INFO_OS_GET_TIME();
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}
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}
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void read_timer_end_of_swap(void)
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{
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if (arch_timing_value_swap_end == 1U) {
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TIMING_INFO_PRE_READ();
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arch_timing_value_swap_end = 2U;
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arch_timing_value_swap_common =
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(u64_t)TIMING_INFO_OS_GET_TIME();
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}
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}
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/* ARM processors read current value of time through sysTick timer
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* and nrf soc read it though timer
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*/
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void read_timer_start_of_isr(void)
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{
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TIMING_INFO_PRE_READ();
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arch_timing_irq_start = (u32_t) TIMING_INFO_GET_TIMER_VALUE();
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}
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void read_timer_end_of_isr(void)
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{
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TIMING_INFO_PRE_READ();
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arch_timing_irq_end = (u32_t) TIMING_INFO_GET_TIMER_VALUE();
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}
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void read_timer_start_of_tick_handler(void)
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{
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TIMING_INFO_PRE_READ();
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arch_timing_tick_start = (u32_t)TIMING_INFO_GET_TIMER_VALUE();
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}
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void read_timer_end_of_tick_handler(void)
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{
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TIMING_INFO_PRE_READ();
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arch_timing_tick_end = (u32_t) TIMING_INFO_GET_TIMER_VALUE();
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}
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void read_timer_end_of_userspace_enter(void)
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{
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TIMING_INFO_PRE_READ();
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arch_timing_enter_user_mode_end = (u32_t)TIMING_INFO_GET_TIMER_VALUE();
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}
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