67 lines
3.3 KiB
C
67 lines
3.3 KiB
C
/**
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* \file
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*
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* \brief Instance description for UART1
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*
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* Copyright (c) 2016 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
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*
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* \license_start
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*
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* \page License
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \license_stop
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*
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*/
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#ifndef _SAME70_UART1_INSTANCE_H_
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#define _SAME70_UART1_INSTANCE_H_
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/* ========== Register definition for UART1 peripheral ========== */
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#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_UART1_CR (0x400E0A00) /**< (UART1) Control Register */
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#define REG_UART1_MR (0x400E0A04) /**< (UART1) Mode Register */
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#define REG_UART1_IER (0x400E0A08) /**< (UART1) Interrupt Enable Register */
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#define REG_UART1_IDR (0x400E0A0C) /**< (UART1) Interrupt Disable Register */
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#define REG_UART1_IMR (0x400E0A10) /**< (UART1) Interrupt Mask Register */
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#define REG_UART1_SR (0x400E0A14) /**< (UART1) Status Register */
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#define REG_UART1_RHR (0x400E0A18) /**< (UART1) Receive Holding Register */
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#define REG_UART1_THR (0x400E0A1C) /**< (UART1) Transmit Holding Register */
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#define REG_UART1_BRGR (0x400E0A20) /**< (UART1) Baud Rate Generator Register */
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#define REG_UART1_CMPR (0x400E0A24) /**< (UART1) Comparison Register */
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#define REG_UART1_WPMR (0x400E0AE4) /**< (UART1) Write Protection Mode Register */
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#else
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#define REG_UART1_CR (*(__O uint32_t*)0x400E0A00U) /**< (UART1) Control Register */
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#define REG_UART1_MR (*(__IO uint32_t*)0x400E0A04U) /**< (UART1) Mode Register */
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#define REG_UART1_IER (*(__O uint32_t*)0x400E0A08U) /**< (UART1) Interrupt Enable Register */
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#define REG_UART1_IDR (*(__O uint32_t*)0x400E0A0CU) /**< (UART1) Interrupt Disable Register */
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#define REG_UART1_IMR (*(__I uint32_t*)0x400E0A10U) /**< (UART1) Interrupt Mask Register */
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#define REG_UART1_SR (*(__I uint32_t*)0x400E0A14U) /**< (UART1) Status Register */
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#define REG_UART1_RHR (*(__I uint32_t*)0x400E0A18U) /**< (UART1) Receive Holding Register */
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#define REG_UART1_THR (*(__O uint32_t*)0x400E0A1CU) /**< (UART1) Transmit Holding Register */
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#define REG_UART1_BRGR (*(__IO uint32_t*)0x400E0A20U) /**< (UART1) Baud Rate Generator Register */
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#define REG_UART1_CMPR (*(__IO uint32_t*)0x400E0A24U) /**< (UART1) Comparison Register */
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#define REG_UART1_WPMR (*(__IO uint32_t*)0x400E0AE4U) /**< (UART1) Write Protection Mode Register */
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#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance Parameter definitions for UART1 peripheral ========== */
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#define UART1_INSTANCE_ID 8
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#define UART1_DMAC_ID_TX 22
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#define UART1_DMAC_ID_RX 23
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#endif /* _SAME70_UART1_INSTANCE_ */
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