69 lines
3.5 KiB
C
69 lines
3.5 KiB
C
/**
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* \file
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*
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* \brief Instance description for RTC
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*
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* Copyright (c) 2016 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
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*
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* \license_start
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*
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* \page License
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \license_stop
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*
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*/
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#ifndef _SAME70_RTC_INSTANCE_H_
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#define _SAME70_RTC_INSTANCE_H_
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/* ========== Register definition for RTC peripheral ========== */
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#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_RTC_CR (0x400E1860) /**< (RTC) Control Register */
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#define REG_RTC_MR (0x400E1864) /**< (RTC) Mode Register */
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#define REG_RTC_TIMR (0x400E1868) /**< (RTC) Time Register */
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#define REG_RTC_CALR (0x400E186C) /**< (RTC) Calendar Register */
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#define REG_RTC_TIMALR (0x400E1870) /**< (RTC) Time Alarm Register */
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#define REG_RTC_CALALR (0x400E1874) /**< (RTC) Calendar Alarm Register */
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#define REG_RTC_SR (0x400E1878) /**< (RTC) Status Register */
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#define REG_RTC_SCCR (0x400E187C) /**< (RTC) Status Clear Command Register */
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#define REG_RTC_IER (0x400E1880) /**< (RTC) Interrupt Enable Register */
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#define REG_RTC_IDR (0x400E1884) /**< (RTC) Interrupt Disable Register */
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#define REG_RTC_IMR (0x400E1888) /**< (RTC) Interrupt Mask Register */
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#define REG_RTC_VER (0x400E188C) /**< (RTC) Valid Entry Register */
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#define REG_RTC_WPMR (0x400E1944) /**< (RTC) Write Protection Mode Register */
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#else
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#define REG_RTC_CR (*(__IO uint32_t*)0x400E1860U) /**< (RTC) Control Register */
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#define REG_RTC_MR (*(__IO uint32_t*)0x400E1864U) /**< (RTC) Mode Register */
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#define REG_RTC_TIMR (*(__IO uint32_t*)0x400E1868U) /**< (RTC) Time Register */
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#define REG_RTC_CALR (*(__IO uint32_t*)0x400E186CU) /**< (RTC) Calendar Register */
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#define REG_RTC_TIMALR (*(__IO uint32_t*)0x400E1870U) /**< (RTC) Time Alarm Register */
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#define REG_RTC_CALALR (*(__IO uint32_t*)0x400E1874U) /**< (RTC) Calendar Alarm Register */
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#define REG_RTC_SR (*(__I uint32_t*)0x400E1878U) /**< (RTC) Status Register */
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#define REG_RTC_SCCR (*(__O uint32_t*)0x400E187CU) /**< (RTC) Status Clear Command Register */
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#define REG_RTC_IER (*(__O uint32_t*)0x400E1880U) /**< (RTC) Interrupt Enable Register */
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#define REG_RTC_IDR (*(__O uint32_t*)0x400E1884U) /**< (RTC) Interrupt Disable Register */
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#define REG_RTC_IMR (*(__I uint32_t*)0x400E1888U) /**< (RTC) Interrupt Mask Register */
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#define REG_RTC_VER (*(__I uint32_t*)0x400E188CU) /**< (RTC) Valid Entry Register */
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#define REG_RTC_WPMR (*(__IO uint32_t*)0x400E1944U) /**< (RTC) Write Protection Mode Register */
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#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance Parameter definitions for RTC peripheral ========== */
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#define RTC_INSTANCE_ID 2
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#endif /* _SAME70_RTC_INSTANCE_ */
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