324 lines
6.9 KiB
Plaintext
324 lines
6.9 KiB
Plaintext
/*
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* Copyright (c) 2018 - 2020 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "litex,vexriscv", "litex-dev";
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model = "litex,vexriscv";
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chosen {
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zephyr,entropy = &prbs0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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clock-frequency = <100000000>;
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compatible = "riscv";
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device_type = "cpu";
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reg = <0>;
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riscv,isa = "rv32imac";
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status = "okay";
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timebase-frequency = <32768>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "litex,vexriscv";
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ranges;
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intc0: interrupt-controller@bc0 {
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compatible = "vexriscv-intc0";
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#address-cells = <0>;
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xbc0 0x4 0xfc0 0x4>;
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reg-names = "irq_mask", "irq_pending";
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riscv,max-priority = <7>;
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};
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uart0: serial@e0001800 {
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compatible = "litex,uart0";
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interrupt-parent = <&intc0>;
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interrupts = <2 10>;
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reg = <0xe0001800 0x4
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0xe0001804 0x4
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0xe0001808 0x4
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0xe000180c 0x4
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0xe0001810 0x4
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0xe0001814 0x4
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0xe0001818 0x4
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0xe000181c 0x4>;
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reg-names =
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"rxtx",
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"txfull",
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"rxempty",
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"ev_status",
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"ev_pending",
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"ev_enable",
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"txempty",
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"rxfull";
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status = "disabled";
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};
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spi0: spi@e0002000 {
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compatible = "litex,spi";
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reg = <0xe0002000 0x4
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0xe0002004 0x4
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0xe0002008 0x4
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0xe000200c 0x4
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0xe0002010 0x4
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0xe0002014 0x4>;
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reg-names = "control",
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"status",
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"mosi",
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"miso",
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"cs",
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"loopback";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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timer0: timer@e0002800 {
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compatible = "litex,timer0";
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interrupt-parent = <&intc0>;
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interrupts = <1 0>;
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reg = <0xe0002800 0x4
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0xe0002804 0x4
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0xe0002808 0x4
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0xe000280c 0x4
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0xe0002810 0x4
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0xe0002814 0x4
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0xe0002818 0x4
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0xe000281c 0x4
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0xe0002820 0x4
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0xe0002824 0x8>;
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reg-names =
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"load",
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"reload",
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"en",
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"update_value",
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"value",
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"ev_status",
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"ev_pending",
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"ev_enable",
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"uptime_latch",
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"uptime_cycles";
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status = "disabled";
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};
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eth0: ethernet@e0009800 {
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compatible = "litex,eth0";
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interrupt-parent = <&intc0>;
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interrupts = <3 0>;
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reg = <0xe0009800 0x4
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0xe0009804 0x4
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0xe0009808 0x4
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0xe000980c 0x4
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0xe0009810 0x4
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0xe0009814 0x4
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0xe0009818 0x4
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0xe000981c 0x4
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0xe0009820 0x4
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0xe0009824 0x4
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0xe0009828 0x4
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0xe000982c 0x4
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0xe0009830 0x4
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0xe0009834 0x4
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0xb0000000 0x2000>;
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local-mac-address = [10 e2 d5 00 00 02];
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reg-names = "rx_slot",
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"rx_length",
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"rx_errors",
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"rx_ev_status",
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"rx_ev_pending",
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"rx_ev_enable",
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"tx_start",
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"tx_ready",
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"tx_level",
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"tx_slot",
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"tx_length",
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"tx_ev_status",
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"tx_ev_pending",
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"tx_ev_enable",
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"buffers";
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status = "disabled";
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};
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dna0: dna@e0003800 {
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compatible = "litex,dna0";
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/* DNA data is 57-bits long,
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so it requires 8 bytes.
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In LiteX each 32-bit register holds
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only a single byte of meaningful data,
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hence 8 registers. */
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reg = <0xe0003800 0x20>;
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reg-names = "mem";
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status = "disabled";
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};
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i2c0: i2c@e0005000 {
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compatible = "litex,i2c";
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reg = <0xe0005000 0x4 0xe0005004 0x4>;
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reg-names = "write", "read";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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gpio_out: gpio@e0005800 {
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compatible = "litex,gpio";
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reg = <0xe0005800 0x4>;
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reg-names = "control";
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ngpios = <4>;
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port-is-output;
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status = "disabled";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio_in: gpio@e0006000 {
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compatible = "litex,gpio";
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reg = <0xe0006000 0x4
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0xe0006004 0x4
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0xe0006008 0x4
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0xe0006010 0x4
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0xe0006014 0x4>;
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interrupt-parent = <&intc0>;
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interrupts = <4 2>;
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reg-names = "base",
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"irq_mode",
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"irq_edge",
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"irq_pend",
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"irq_en";
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ngpios = <4>;
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status = "disabled";
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gpio-controller;
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#gpio-cells = <2>;
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};
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prbs0: prbs@e0006800 {
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compatible = "litex,prbs";
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reg = <0xe0006800 0x4>;
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reg-names = "status";
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status = "disabled";
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};
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pwm0: pwm@e0007000 {
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compatible = "litex,pwm";
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reg = <0xe0007000 0x4 0xe0007004 0x10 0xe0007014 0x10>;
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reg-names = "enable", "width", "period";
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status = "disabled";
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#pwm-cells = <2>;
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};
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i2s_rx: i2s_rx@e000a800 {
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compatible = "litex,i2s";
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reg = <0xe000a800 0x4
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0xe000a804 0x4
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0xe000a808 0x4
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0xe000a80c 0x4
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0xe000a810 0x4
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0xe000a814 0x4
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0xb1000000 0x40000>;
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interrupt-parent = <&intc0>;
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interrupts = <6 2>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "ev_status",
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"ev_pending",
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"ev_enable",
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"rx_ctl",
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"rx_stat",
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"rx_conf",
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"fifo";
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fifo_depth = <256>;
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status = "disabled";
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};
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i2s_tx: i2s_tx@e000b000 {
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compatible = "litex,i2s";
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reg = <0xe000b000 0x4
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0xe000b004 0x4
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0xe000b008 0x4
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0xe000b00c 0x4
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0xe000b010 0x4
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0xe000b014 0x4
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0xb2000000 0x40000>;
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interrupt-parent = <&intc0>;
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interrupts = <7 2>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "ev_status",
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"ev_pending",
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"ev_enable",
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"tx_ctl",
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"tx_stat",
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"tx_conf",
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"fifo";
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fifo_depth = <256>;
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status = "disabled";
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};
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clock-outputs {
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#address-cells = <1>;
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#size-cells = <0>;
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clk0: clock-controller@0 {
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#clock-cells = <1>;
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reg = <0>;
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compatible = "litex,clkout";
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clock-output-names = "CLK_0";
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litex,clock-frequency = <11289600>;
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litex,clock-phase = <0>;
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litex,clock-duty-num = <1>;
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litex,clock-duty-den = <2>;
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litex,clock-margin = <1>;
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litex,clock-margin-exp = <2>;
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status = "disabled";
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};
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clk1: clock-controller@1 {
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#clock-cells = <1>;
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reg = <1>;
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compatible = "litex,clkout";
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clock-output-names = "CLK_1";
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litex,clock-frequency = <22579200>;
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litex,clock-phase = <0>;
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litex,clock-duty-num = <1>;
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litex,clock-duty-den = <2>;
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litex,clock-margin = <1>;
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litex,clock-margin-exp = <2>;
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status = "disabled";
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};
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};
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clock0: clock@e0004800 {
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compatible = "litex,clk";
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reg = <0xe0004800 0x4
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0xe0004804 0x4
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0xe0004808 0x4
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0xe000480c 0x4
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0xe0004810 0x4
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0xe0004814 0x4
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0xe0004818 0x4
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0xe000481c 0x4>;
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reg-names = "drp_reset",
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"drp_locked",
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"drp_read",
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"drp_write",
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"drp_drdy",
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"drp_adr",
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"drp_dat_w",
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"drp_dat_r";
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#clock-cells = <1>;
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clocks = <&clk0 0>, <&clk1 1>;
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clock-output-names = "CLK_0", "CLK_1";
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litex,lock-timeout = <10>;
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litex,drdy-timeout = <10>;
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litex,sys-clock-frequency = <100000000>;
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litex,divclk-divide-min = <1>;
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litex,divclk-divide-max = <107>;
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litex,clkfbout-mult-min = <2>;
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litex,clkfbout-mult-max = <65>;
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litex,vco-freq-min = <600000000>;
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litex,vco-freq-max = <1200000000>;
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litex,clkout-divide-min = <1>;
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litex,clkout-divide-max = <126>;
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litex,vco-margin = <0>;
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status = "disabled";
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};
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};
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};
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