93 lines
2.8 KiB
YAML
93 lines
2.8 KiB
YAML
# Copyright (c) 2022 NXP
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# SPDX-License-Identifier: Apache-2.0
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description: |
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The node has the 'pinctrl' node label set in MCUX RT SoC's devicetree. These
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nodes can be autogenerated using the MCUXpresso config tools combined with
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the rt_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
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fields in a group select the pins to be configured, and the remaining
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devicetree properties set configuration values for those pins
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for example, here is an group configuring LPUART1 pins:
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group0 {
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pinmux = <&iomuxc_gpio_ad_25_lpuart1_rxd>,
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<&iomuxc_gpio_ad_24_lpuart1_txd>;
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drive-strength = "high";
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slew-rate = "slow";
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};
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This will select GPIO_AD_25 as LPUART1 RX, and GPIO_AD_24 as LPUART1 TX.
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Both pins will be configured with a weak latch, high drive strength,
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and slow slew rates.
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Note that the soc level iomuxc dts file can be examined to find the possible
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pinmux options. Here are the affects of each property on the
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IOMUXC SW_PAD_CTL register:
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drive-open-drain: ODE/ODE_LPSR=1
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input-enable: SION=1 (in SW_MUX_CTL_PAD register)
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bias-pull-down: PUE=1, PUS=0
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bias-pull-up: PUE=1, PUS=1
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bias-disable: PULL=11 (in supported registers)
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slew-rate: SRE=<enum_idx>
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drive-strength: DSE=<enum_idx>
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If only required properties are supplied, the pin will have the following
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configuration:
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ODE=0
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SION=0
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PUE=0
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PUS=0
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SRE=0
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DSE=0
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For registers with PDVR and PULL fields, these are the defaults:
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PULL=11
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PDRV=0
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compatible: "nxp,mcux-rt11xx-pinctrl"
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include:
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- name: base.yaml
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- name: pincfg-node-group.yaml
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child-binding:
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child-binding:
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property-allowlist:
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- drive-open-drain
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- input-enable
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- bias-disable
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- bias-pull-down
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- bias-pull-up
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child-binding:
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description: MCUX RT pin controller pin group
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child-binding:
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description: |
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MCUX RT pin controller pin configuration node.
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properties:
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pinmux:
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required: true
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type: phandles
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description: |
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Pin mux selections for this group. See the soc level iomuxc DTSI file
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for a defined list of these options.
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drive-strength:
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required: false
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type: string
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enum:
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- "normal"
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- "high"
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description: |
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Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
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0 (normal) - sets pin to normal drive strength
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1 (high) - sets pin to high drive strength
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slew-rate:
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required: false
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type: string
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enum:
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- "fast"
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- "slow"
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description: |
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Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
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0 (fast) — Fast Slew Rate
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1 (slow) — Slow Slew Rate
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