377 lines
8.3 KiB
Plaintext
377 lines
8.3 KiB
Plaintext
/*
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* Copyright 2022 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv8-r.dtsi>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-r52";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-r52";
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reg = <1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-r52";
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reg = <2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-r52";
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reg = <3>;
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};
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cpu@4 {
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device_type = "cpu";
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compatible = "arm,cortex-r52";
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reg = <4>;
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};
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cpu@5 {
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device_type = "cpu";
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compatible = "arm,cortex-r52";
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reg = <5>;
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};
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cpu@6 {
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device_type = "cpu";
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compatible = "arm,cortex-r52";
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reg = <6>;
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};
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cpu@7 {
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device_type = "cpu";
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compatible = "arm,cortex-r52";
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reg = <7>;
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};
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};
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arch_timer: timer {
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compatible = "arm,armv8_timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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};
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/* Dummy pinctrl node, filled with pin mux options at board level */
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pinctrl: pinctrl {
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compatible = "nxp,s32ze-pinctrl";
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status = "okay";
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};
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soc {
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interrupt-parent = <&gic>;
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gic: interrupt-controller@47800000 {
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compatible = "arm,gic";
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reg = <0x47800000 0x10000>,
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<0x47900000 0x80000>;
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interrupt-controller;
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#interrupt-cells = <4>;
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status = "okay";
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};
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sram0: memory@31780000 {
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compatible = "mmio-sram";
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reg = <0x31780000 DT_SIZE_M(1)>;
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};
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sram1: memory@35780000 {
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compatible = "mmio-sram";
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reg = <0x35780000 DT_SIZE_M(1)>;
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};
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uart0: uart@40170000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x40170000 0x1000>;
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interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart1: uart@40180000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x40180000 0x1000>;
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interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart2: uart@40190000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x40190000 0x1000>;
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interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart3: uart@40970000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x40970000 0x1000>;
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interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart4: uart@40980000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x40980000 0x1000>;
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interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart5: uart@40990000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x40990000 0x1000>;
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interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart6: uart@42170000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x42170000 0x1000>;
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interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart7: uart@42180000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x42180000 0x1000>;
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interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart8: uart@42190000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x42190000 0x1000>;
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart9: uart@42980000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x42980000 0x1000>;
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interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart10: uart@42990000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x42990000 0x1000>;
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interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart11: uart@429a0000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x429a0000 0x1000>;
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interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart12: uart@40330000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x40330000 0x1000>;
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interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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siul2_0: siul2@40520000 {
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reg = <0x40520000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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gpioa: gpio@40521702 {
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compatible = "nxp,s32-gpio";
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reg = <0x40521702 0x02>, <0x40520240 0x40>;
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reg-names = "pgpdo", "mscr";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpiob: gpio@40521700 {
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compatible = "nxp,s32-gpio";
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reg = <0x40521700 0x02>, <0x40520280 0x40>;
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reg-names = "pgpdo", "mscr";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <15>;
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status = "disabled";
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};
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gpioo: gpio@40521716 {
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compatible = "nxp,s32-gpio";
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reg = <0x40521716 0x02>, <0x405204c0 0x40>;
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reg-names = "pgpdo", "mscr";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <14>;
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gpio-reserved-ranges = <0 10>;
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status = "disabled";
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};
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};
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siul2_1: siul2@40d20000 {
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reg = <0x40d20000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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gpioc: gpio@40d21700 {
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compatible = "nxp,s32-gpio";
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reg = <0x40d21700 0x02>, <0x40d20280 0x40>;
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reg-names = "pgpdo", "mscr";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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gpio-reserved-ranges = <0 15>;
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status = "disabled";
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};
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gpiod: gpio@40d21706 {
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compatible = "nxp,s32-gpio";
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reg = <0x40d21706 0x02>, <0x40d202c0 0x40>;
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reg-names = "pgpdo", "mscr";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpioe: gpio@40d21704 {
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compatible = "nxp,s32-gpio";
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reg = <0x40d21704 0x02>, <0x40d20300 0x40>;
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reg-names = "pgpdo", "mscr";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpiof: gpio@40d2170a {
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compatible = "nxp,s32-gpio";
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reg = <0x40d2170a 0x02>, <0x40d20340 0x40>;
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reg-names = "pgpdo", "mscr";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpiog: gpio@40d21708 {
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compatible = "nxp,s32-gpio";
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reg = <0x40d21708 0x02>, <0x40d20380 0x40>;
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reg-names = "pgpdo", "mscr";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <12>;
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status = "disabled";
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};
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};
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siul2_3: siul2@41d20000 {
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reg = <0x41d20000 0x10000>;
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};
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siul2_4: siul2@42520000 {
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reg = <0x42520000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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gpioh: gpio@42521708 {
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compatible = "nxp,s32-gpio";
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reg = <0x42521708 0x02>, <0x42520380 0x40>;
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reg-names = "pgpdo", "mscr";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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gpio-reserved-ranges = <0 12>;
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status = "disabled";
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};
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gpioi: gpio@4252170e {
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compatible = "nxp,s32-gpio";
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reg = <0x4252170e 0x02>, <0x425203c0 0x40>;
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reg-names = "pgpdo", "mscr";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpioj: gpio@4252170c {
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compatible = "nxp,s32-gpio";
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reg = <0x4252170c 0x02>, <0x42520400 0x40>;
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reg-names = "pgpdo", "mscr";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpiok: gpio@42521712 {
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compatible = "nxp,s32-gpio";
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reg = <0x42521712 0x02>, <0x42520440 0x40>;
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reg-names = "pgpdo", "mscr";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpiol: gpio@42521710 {
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compatible = "nxp,s32-gpio";
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reg = <0x42521710 0x02>, <0x42520480 0x40>;
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reg-names = "disr0", "direr0";
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reg-names = "pgpdo", "mscr";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <2>;
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status = "disabled";
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};
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};
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siul2_5: siul2@42d20000 {
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reg = <0x42d20000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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gpiom: gpio@42d21710 {
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compatible = "nxp,s32-gpio";
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reg = <0x42d21710 0x02>, <0x42d20480 0x40>;
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reg-names = "pgpdo", "mscr";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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gpio-reserved-ranges = <0 2>;
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status = "disabled";
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};
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gpion: gpio@42d21716 {
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compatible = "nxp,s32-gpio";
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reg = <0x42d21716 0x02>, <0x42d204c0 0x40>;
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reg-names = "pgpdo", "mscr";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <10>;
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status = "disabled";
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};
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};
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};
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};
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