401 lines
13 KiB
C
401 lines
13 KiB
C
/*
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* Copyright (c) 2020 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nuvoton_npcx_miwu
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/**
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* @file
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* @brief Nuvoton NPCX MIWU driver
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*
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* The device Multi-Input Wake-Up Unit (MIWU) supports the Nuvoton embedded
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* controller (EC) to exit 'Sleep' or 'Deep Sleep' power state which allows chip
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* has better power consumption. Also, it provides signal conditioning such as
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* 'Level' and 'Edge' trigger type and grouping of external interrupt sources
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* of NVIC. The NPCX series has three identical MIWU modules: MIWU0, MIWU1,
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* MIWU2. Together, they support a total of over 140 internal and/or external
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* wake-up input (WUI) sources.
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*
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* This driver uses device tree files to present the relationship between
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* MIWU and the other devices in different npcx series. For npcx7 series,
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* it include:
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* 1. npcxn-miwus-wui-map.dtsi: it presents relationship between wake-up inputs
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* (WUI) and its source device such as gpio, timer, eSPI VWs and so on.
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* 2. npcxn-miwus-int-map.dtsi: it presents relationship between MIWU group
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* and NVIC interrupt in npcx series. Please notice it isn't 1-to-1 mapping.
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* For example, here is the mapping between miwu0's group a & d and IRQ7:
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*
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* map_miwu0_groups: {
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* parent = <&miwu0>;
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* group_ad0: group_ad0_map {
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* irq = <7>;
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* group_mask = <0x09>;
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* };
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* ...
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* };
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*
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* It will connect IRQ 7 and intc_miwu_isr0() with the argument, group_mask,
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* by IRQ_CONNECT() during driver initialization function. With group_mask,
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* 0x09, the driver checks the pending bits of group a and group d in ISR.
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* Then it will execute related callback functions if they have been
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* registered properly.
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*
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* INCLUDE FILES: soc_miwu.h
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*
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*/
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#include <zephyr/device.h>
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#include <zephyr/kernel.h>
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#include <soc.h>
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#include <zephyr/sys/__assert.h>
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#include <zephyr/irq_nextlevel.h>
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#include <zephyr/drivers/gpio.h>
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#include "soc_miwu.h"
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#include "soc_gpio.h"
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#include <zephyr/logging/log.h>
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#include <zephyr/irq.h>
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LOG_MODULE_REGISTER(intc_miwu, LOG_LEVEL_ERR);
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/* MIWU module instances */
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#define NPCX_MIWU_DEV(inst) DEVICE_DT_INST_GET(inst),
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static const struct device *const miwu_devs[] = {
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DT_INST_FOREACH_STATUS_OKAY(NPCX_MIWU_DEV)
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};
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BUILD_ASSERT(ARRAY_SIZE(miwu_devs) == NPCX_MIWU_TABLE_COUNT,
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"Size of miwu_devs array must equal to NPCX_MIWU_TABLE_COUNT");
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/* Driver config */
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struct intc_miwu_config {
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/* miwu controller base address */
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uintptr_t base;
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/* index of miwu controller */
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uint8_t index;
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};
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/* Callback functions list for GPIO wake-up inputs */
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sys_slist_t cb_list_gpio;
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/*
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* Callback functions list for the generic hardware modules wake-up inputs
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* such as timer, uart, i2c, host interface and so on.
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*/
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sys_slist_t cb_list_generic;
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BUILD_ASSERT(sizeof(struct miwu_io_callback) == sizeof(struct gpio_callback),
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"Size of struct miwu_io_callback must equal to struct gpio_callback");
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BUILD_ASSERT(sizeof(struct miwu_io_params) == sizeof(gpio_port_pins_t),
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"Size of struct miwu_io_params must equal to struct gpio_port_pins_t");
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/* MIWU local functions */
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static void intc_miwu_dispatch_gpio_isr(uint8_t wui_table,
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uint8_t wui_group, uint8_t wui_bit)
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{
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struct miwu_io_callback *cb, *tmp;
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SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&cb_list_gpio, cb, tmp, node) {
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/* Pending bit, group and table match the wui item in list */
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if (cb->params.wui.table == wui_table
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&& cb->params.wui.group == wui_group
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&& cb->params.wui.bit == wui_bit) {
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__ASSERT(cb->handler, "No GPIO callback handler!");
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/*
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* Execute GPIO callback and the other callback might
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* match the same wui item.
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*/
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cb->handler(npcx_get_gpio_dev(cb->params.gpio_port),
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(struct gpio_callback *)cb,
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cb->params.pin_mask);
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}
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}
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}
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static void intc_miwu_dispatch_generic_isr(uint8_t wui_table,
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uint8_t wui_group, uint8_t wui_bit)
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{
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struct miwu_dev_callback *cb, *tmp;
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SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&cb_list_generic, cb, tmp, node) {
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/* Pending bit, group and table match the wui item in list */
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if (cb->wui.table == wui_table
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&& cb->wui.group == wui_group
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&& cb->wui.bit == wui_bit) {
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__ASSERT(cb->handler, "No Generic callback handler!");
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/*
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* Execute generic callback and the other callback might
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* match the same wui item.
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*/
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cb->handler(cb->source, &cb->wui);
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}
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}
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}
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static void intc_miwu_isr_pri(int wui_table, int wui_group)
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{
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int wui_bit;
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const struct intc_miwu_config *config = miwu_devs[wui_table]->config;
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const uint32_t base = config->base;
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uint8_t mask = NPCX_WKPND(base, wui_group) & NPCX_WKEN(base, wui_group);
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/* Clear pending bits before dispatch ISR */
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if (mask) {
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NPCX_WKPCL(base, wui_group) = mask;
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}
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for (wui_bit = 0; wui_bit < 8; wui_bit++) {
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if (mask & BIT(wui_bit)) {
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LOG_DBG("miwu_isr %d %d %d!\n", wui_table,
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wui_group, wui_bit);
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/* Dispatch registered gpio and generic isrs */
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intc_miwu_dispatch_gpio_isr(wui_table,
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wui_group, wui_bit);
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intc_miwu_dispatch_generic_isr(wui_table,
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wui_group, wui_bit);
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}
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}
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}
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/* Platform specific MIWU functions */
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void npcx_miwu_irq_enable(const struct npcx_wui *wui)
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{
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const struct intc_miwu_config *config = miwu_devs[wui->table]->config;
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const uint32_t base = config->base;
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NPCX_WKEN(base, wui->group) |= BIT(wui->bit);
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}
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void npcx_miwu_irq_disable(const struct npcx_wui *wui)
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{
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const struct intc_miwu_config *config = miwu_devs[wui->table]->config;
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const uint32_t base = config->base;
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NPCX_WKEN(base, wui->group) &= ~BIT(wui->bit);
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}
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void npcx_miwu_io_enable(const struct npcx_wui *wui)
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{
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const struct intc_miwu_config *config = miwu_devs[wui->table]->config;
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const uint32_t base = config->base;
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NPCX_WKINEN(base, wui->group) |= BIT(wui->bit);
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}
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void npcx_miwu_io_disable(const struct npcx_wui *wui)
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{
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const struct intc_miwu_config *config = miwu_devs[wui->table]->config;
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const uint32_t base = config->base;
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NPCX_WKINEN(base, wui->group) &= ~BIT(wui->bit);
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}
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bool npcx_miwu_irq_get_state(const struct npcx_wui *wui)
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{
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const struct intc_miwu_config *config = miwu_devs[wui->table]->config;
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const uint32_t base = config->base;
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return IS_BIT_SET(NPCX_WKEN(base, wui->group), wui->bit);
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}
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bool npcx_miwu_irq_get_and_clear_pending(const struct npcx_wui *wui)
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{
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const struct intc_miwu_config *config = miwu_devs[wui->table]->config;
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const uint32_t base = config->base;
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bool pending = IS_BIT_SET(NPCX_WKPND(base, wui->group), wui->bit);
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if (pending) {
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NPCX_WKPCL(base, wui->group) = BIT(wui->bit);
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}
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return pending;
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}
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int npcx_miwu_interrupt_configure(const struct npcx_wui *wui,
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enum miwu_int_mode mode, enum miwu_int_trig trig)
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{
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const struct intc_miwu_config *config = miwu_devs[wui->table]->config;
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const uint32_t base = config->base;
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uint8_t pmask = BIT(wui->bit);
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/* Disable interrupt of wake-up input source before configuring it */
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npcx_miwu_irq_disable(wui);
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/* Handle interrupt for level trigger */
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if (mode == NPCX_MIWU_MODE_LEVEL) {
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/* Set detection mode to level */
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NPCX_WKMOD(base, wui->group) |= pmask;
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switch (trig) {
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/* Enable interrupting on level high */
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case NPCX_MIWU_TRIG_HIGH:
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NPCX_WKEDG(base, wui->group) &= ~pmask;
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break;
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/* Enable interrupting on level low */
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case NPCX_MIWU_TRIG_LOW:
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NPCX_WKEDG(base, wui->group) |= pmask;
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break;
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default:
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return -EINVAL;
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}
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/* Handle interrupt for edge trigger */
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} else {
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/* Set detection mode to edge */
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NPCX_WKMOD(base, wui->group) &= ~pmask;
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switch (trig) {
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/* Handle interrupting on falling edge */
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case NPCX_MIWU_TRIG_LOW:
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NPCX_WKAEDG(base, wui->group) &= ~pmask;
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NPCX_WKEDG(base, wui->group) |= pmask;
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break;
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/* Handle interrupting on rising edge */
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case NPCX_MIWU_TRIG_HIGH:
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NPCX_WKAEDG(base, wui->group) &= ~pmask;
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NPCX_WKEDG(base, wui->group) &= ~pmask;
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break;
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/* Handle interrupting on both edges */
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case NPCX_MIWU_TRIG_BOTH:
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/* Enable any edge */
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NPCX_WKAEDG(base, wui->group) |= pmask;
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break;
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default:
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return -EINVAL;
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}
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}
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/* Enable wake-up input sources */
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NPCX_WKINEN(base, wui->group) |= pmask;
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/*
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* Clear pending bit since it might be set if WKINEN bit is
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* changed.
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*/
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NPCX_WKPCL(base, wui->group) |= pmask;
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return 0;
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}
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void npcx_miwu_init_gpio_callback(struct miwu_io_callback *callback,
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const struct npcx_wui *io_wui, int port)
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{
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/* Initialize WUI and GPIO settings in unused bits field */
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callback->params.wui.table = io_wui->table;
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callback->params.wui.group = io_wui->group;
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callback->params.wui.bit = io_wui->bit;
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callback->params.gpio_port = port;
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}
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void npcx_miwu_init_dev_callback(struct miwu_dev_callback *callback,
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const struct npcx_wui *dev_wui,
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miwu_dev_callback_handler_t handler,
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const struct device *source)
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{
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/* Initialize WUI and input device settings */
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callback->wui.table = dev_wui->table;
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callback->wui.group = dev_wui->group;
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callback->wui.bit = dev_wui->bit;
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callback->handler = handler;
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callback->source = source;
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}
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int npcx_miwu_manage_gpio_callback(struct miwu_io_callback *cb, bool set)
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{
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if (!sys_slist_is_empty(&cb_list_gpio)) {
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if (!sys_slist_find_and_remove(&cb_list_gpio, &cb->node)) {
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if (!set) {
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return -EINVAL;
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}
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}
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}
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if (set) {
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sys_slist_prepend(&cb_list_gpio, &cb->node);
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}
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return 0;
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}
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int npcx_miwu_manage_dev_callback(struct miwu_dev_callback *cb, bool set)
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{
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if (!sys_slist_is_empty(&cb_list_generic)) {
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if (!sys_slist_find_and_remove(&cb_list_generic, &cb->node)) {
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if (!set) {
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return -EINVAL;
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}
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}
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}
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if (set) {
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sys_slist_prepend(&cb_list_generic, &cb->node);
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}
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return 0;
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}
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/* MIWU driver registration */
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#define NPCX_MIWU_ISR_FUNC(index) _CONCAT(intc_miwu_isr, index)
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#define NPCX_MIWU_INIT_FUNC(inst) _CONCAT(intc_miwu_init, inst)
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#define NPCX_MIWU_INIT_FUNC_DECL(inst) \
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static int intc_miwu_init##inst(const struct device *dev)
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/* MIWU ISR implementation */
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#define NPCX_MIWU_ISR_FUNC_IMPL(inst) \
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static void intc_miwu_isr##inst(void *arg) \
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{ \
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uint8_t grp_mask = (uint32_t)arg; \
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int group = 0; \
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\
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/* Check all MIWU groups belong to the same irq */ \
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do { \
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if (grp_mask & 0x01) \
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intc_miwu_isr_pri(inst, group); \
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group++; \
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grp_mask = grp_mask >> 1; \
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\
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} while (grp_mask != 0); \
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}
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/* MIWU init function implementation */
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#define NPCX_MIWU_INIT_FUNC_IMPL(inst) \
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static int intc_miwu_init##inst(const struct device *dev) \
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{ \
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int i; \
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const struct intc_miwu_config *config = dev->config; \
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const uint32_t base = config->base; \
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\
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/* Clear all MIWUs' pending and enable bits of MIWU device */ \
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for (i = 0; i < NPCX_MIWU_GROUP_COUNT; i++) { \
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NPCX_WKEN(base, i) = 0; \
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NPCX_WKPCL(base, i) = 0xFF; \
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} \
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\
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/* Config IRQ and MWIU group directly */ \
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DT_FOREACH_CHILD(NPCX_DT_NODE_FROM_MIWU_MAP(inst), \
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NPCX_DT_MIWU_IRQ_CONNECT_IMPL_CHILD_FUNC) \
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return 0; \
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} \
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#define NPCX_MIWU_INIT(inst) \
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NPCX_MIWU_INIT_FUNC_DECL(inst); \
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\
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static const struct intc_miwu_config miwu_config_##inst = { \
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.base = DT_REG_ADDR(DT_NODELABEL(miwu##inst)), \
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.index = DT_PROP(DT_NODELABEL(miwu##inst), index), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(inst, \
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NPCX_MIWU_INIT_FUNC(inst), \
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NULL, \
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NULL, &miwu_config_##inst, \
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PRE_KERNEL_1, \
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CONFIG_INTC_INIT_PRIORITY, NULL); \
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\
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NPCX_MIWU_ISR_FUNC_IMPL(inst) \
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\
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NPCX_MIWU_INIT_FUNC_IMPL(inst)
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DT_INST_FOREACH_STATUS_OKAY(NPCX_MIWU_INIT)
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