505 lines
22 KiB
C
505 lines
22 KiB
C
#ifndef ETH_CYCLONEV_HEADER
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#define ETH_CYCLONEV_HEADER
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/*
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* SPDX-License-Identifier: Apache-2.0
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* Copyright (C) 2022, Intel Corporation
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* Description:
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* Driver for the Synopsys DesignWare
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* 3504-0 Universal 10/100/1000 Ethernet MAC (DWC_gmac)
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* specifically designed for Cyclone V SoC DevKit use only.
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/types.h>
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#define alt_replbits_word(dest, msk, src) \
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(sys_write32((sys_read32(dest) & ~(msk)) | ((src) & (msk)), dest))
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#define NB_TX_DESCS CONFIG_ETH_CVSX_NB_TX_DESCS
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#define NB_RX_DESCS CONFIG_ETH_CVSX_NB_RX_DESCS
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#define ETH_BUFFER_SIZE 1536
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/* Descriptor Structure */
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struct eth_cyclonev_dma_desc {
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uint32_t status; /*!< Status */
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uint32_t control_buffer_size; /*!< Control and Buffer1, Buffer2 sizes */
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uint32_t buffer1_addr; /*!< Buffer1 address pointer */
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uint32_t buffer2_next_desc_addr; /*!< Buffer2 or next desc address pointer */
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};
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struct eth_cyclonev_priv {
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mem_addr_t base_addr; /* Base address */
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uint32_t instance;
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uint8_t mac_addr[6];
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uint32_t interrupt_mask;
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struct net_if *iface; /* Zephyr net_if Interface Struct (for interface initialisation) */
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uint32_t tx_current_desc_number;
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uint32_t rx_current_desc_number;
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uint32_t tx_tail;
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uint32_t feature; /* HW feature register */
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/* Tx/Rx Descriptor Rings */
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struct eth_cyclonev_dma_desc tx_desc_ring[NB_TX_DESCS], rx_desc_ring[NB_RX_DESCS];
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uint32_t rxints; /* Tx stats */
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uint32_t txints; /* Rx stats */
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uint8_t rx_buf[ETH_BUFFER_SIZE * NB_RX_DESCS]; /* Receive Buffer */
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uint8_t tx_buf[ETH_BUFFER_SIZE * NB_TX_DESCS]; /* Transmit Buffer */
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struct k_sem free_tx_descs;
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uint8_t running; /* Running state flag */
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uint8_t initialised; /* Initialised state flag */
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};
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/*
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* Reset Manager Regs
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*/
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/* The base address of the Rstmgr register group. */
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#define RSTMGR_BASE 0xffd05000
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/* The byte offset of the ALT_RSTMGR_PERMODRST register from the beginning of
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* the component.
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*/
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#define RSTMGR_PERMODRST_OFST 0x14
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/* The address of the ALT_RSTMGR_PERMODRST register. */
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#define RSTMGR_PERMODRST_ADDR 0xFFD05014
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/* The mask used to set the ALT_RSTMGR_PERMODRST_EMAC0 register field value. */
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#define RSTMGR_PERMODRST_EMAC0_SET_MSK 0x00000001
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/* The mask used to set the ALT_RSTMGR_PERMODRST_EMAC1 register field value. */
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#define RSTMGR_PERMODRST_EMAC1_SET_MSK 0x00000002
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/*
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* System Manager Regs
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*/
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#define SYSMGR_BASE 0xffd08000
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#define SYSMGR_EMAC_ADDR 0xffd08060
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#define SYSMGR_FPGAINTF_INDIV_ADDR 0xffd08004
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/* The byte offset of the SYSMGR_EMAC register from the beginning of the
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* component.
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*/
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#define SYSMGR_EMAC_OFST 0x60
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/* The byte offset of the SYSMGR_FPGAINTF_INDIV register from the beginning of
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* the component.
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*/
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#define SYSMGR_FPGAINTF_INDIV_OFST 0x4
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/*
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* Enumerated value for register field ALT_SYSMGR_EMACn_PHY_INTF_SEL
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*
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*/
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#define SYSMGR_EMAC_PHY_INTF_SEL_E_GMII_MII 0x0
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/*
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* Enumerated value for register field ALT_SYSMGR_EMACn_PHY_INTF_SEL
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*
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*/
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#define SYSMGR_EMAC0_PHY_INTF_SEL_E_RGMII 0x1
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#define SYSMGR_EMAC1_PHY_INTF_SEL_E_RGMII 0x4
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/*
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* Enumerated value for register field ALT_SYSMGR_EMACn_PHY_INTF_SEL
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*
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*/
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#define SYSMGR_EMAC_PHY_INTF_SEL_E_RMII 0x2
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/* The mask used to set the ALT_SYSMGR_EMACn_PHY_INTF_SEL register field value.
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*/
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#define SYSMGR_EMAC0_PHY_INTF_SEL_SET_MSK 0x00000003
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#define SYSMGR_EMAC1_PHY_INTF_SEL_SET_MSK 0x0000000c
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/* The mask used to set the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field
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* value.
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*/
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#define SYSMGR_FPGAINTF_MODULE_EMAC_0_SET_MSK 0x00000004
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/* The mask used to set the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field
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* value.
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*/
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#define SYSMGR_FPGAINTF_MODULE_EMAC_1_SET_MSK 0x00000008
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/*
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* Emac Registers
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*/
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/* Macros */
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#define EMAC_BASE_ADDRESS DT_INST_REG_ADDR(0)
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#define EMAC_DMAGRP_BUS_MODE_ADDR(base) (uint32_t)((base) + EMAC_DMA_MODE_OFST) /* Bus Mode */
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#define EMAC_DMA_RX_DESC_LIST_ADDR(base) (uint32_t)((base) + EMAC_DMA_RX_DESC_LIST_OFST)
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/* Receive Descriptor Address List */
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#define EMAC_DMA_TX_DESC_LIST_ADDR(base) (uint32_t)((base) + EMAC_DMA_TX_DESC_LIST_OFST)
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/* Transceive Descriptor Address List */
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#define EMAC_DMAGRP_OPERATION_MODE_ADDR(base) (uint32_t)((base) + EMAC_DMAGRP_OPERATION_MODE_OFST)
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/* Operation Mode */
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#define EMAC_DMAGRP_STATUS_ADDR(base) (uint32_t)((base) + EMAC_DMAGRP_STATUS_OFST) /* Status */
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#define EMAC_DMAGRP_DEBUG_ADDR(base) (uint32_t)((base) + EMAC_DMAGRP_DEBUG_OFST) /* Debug */
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#define EMAC_DMA_INT_EN_ADDR(base) (uint32_t)((base) + EMAC_DMA_INT_EN_OFST)
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/* Interrupt Enable */
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#define EMAC_DMAGRP_AXI_BUS_MODE_ADDR(base) (uint32_t)((base) + EMAC_DMAGRP_AXI_BUS_MODE_OFST)
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/* AXI Bus Mode */
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#define EMAC_DMAGRP_AHB_OR_AXI_STATUS_ADDR(base) \
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(uint32_t)((base) + EMAC_DMAGRP_AHB_OR_AXI_STATUS_OFST)
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/* AHB or AXI Status */
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#define GMACGRP_CONTROL_STATUS_ADDR(base) \
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(uint32_t)((base) + \
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EMAC_GMACGRP_SGMII_RGMII_SMII_CONTROL_STATUS_OFST) \
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/* SGMII RGMII SMII Control Status */
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#define EMAC_GMAC_INT_MSK_ADDR(base) (uint32_t)((base) + EMAC_GMAC_INT_MSK_OFST)
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/* Interrupt Mask */
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#define EMAC_GMAC_INT_STAT_ADDR(base) (uint32_t)((base) + EMAC_GMAC_INT_STAT_OFST)
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/* Interrupt Status */
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#define GMACGRP_MAC_CONFIG_ADDR(base) (uint32_t)((base) + EMAC_GMACGRP_MAC_CONFIGURATION_OFST)
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/* MAC Configuration */
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#define EMAC_GMACGRP_MAC_FRAME_FILTER_ADDR(base) \
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(uint32_t)((base) + EMAC_GMACGRP_MAC_FRAME_FILTER_OFST)
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/* MAC Frame Filter */
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#define EMAC_GMAC_MAC_ADDR0_HIGH_ADDR(base) (uint32_t)((base) + EMAC_GMAC_MAC_ADDR0_HIGH_OFST)
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/* MAC Address 0 High */
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#define EMAC_GMAC_MAC_ADDR0_LOW_ADDR(base) (uint32_t)((base) + EMAC_GMAC_MAC_ADDR0_LOW_OFST)
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/* MAC Address 0 Low */
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#define EMAC_GMAC_MAC_ADDR_HIGH_ADDR(base, n) (uint32_t)((base) + EMAC_GMAC_MAC_ADDR_HIGH_OFST(n))
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/* MAC Address 0 High */
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#define EMAC_GMAC_MAC_ADDR_LOW_ADDR(base, n) (uint32_t)((base) + EMAC_GMAC_MAC_ADDR_LOW_OFST(n))
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/* MAC Address 0 High */
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#define EMAC_GMAC_GMII_ADDR_ADDR(base) (uint32_t)((base) + EMAC_GMAC_GMII_ADDR_OFST)
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/* GMII Address */
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#define EMAC_GMAC_GMII_DATA_ADDR(base) (uint32_t)((base) + EMAC_GMAC_GMII_DATA_OFST)
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/* GMII Data */
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#define EMAC_DMA_TX_POLL_DEMAND_ADDR(base) (uint32_t)((base) + EMAC_DMA_TX_POLL_DEMAND_OFST)
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/* Transmit Poll Demand */
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#define EMAC_DMA_RX_POLL_DEMAND_ADDR(base) (uint32_t)((base) + EMAC_DMA_RX_POLL_DEMAND_OFST)
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/* Receive Poll Demand */
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#define EMAC_DMA_CURR_HOST_TX_DESC_ADDR(base) (uint32_t)((base) + EMAC_DMA_CURR_HOST_TX_DESC_OFST)
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/* Current Host Transmit Descriptor */
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#define EMAC_DMA_CURR_HOST_RX_DESC_ADDR(base) (uint32_t)((base) + EMAC_DMA_CURR_HOST_RX_DESC_OFST)
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/* Current Host Receive Descriptor */
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#define EMAC_DMA_CURR_HOST_TX_BUFF_ADDR(base) (uint32_t)((base) + EMAC_DMA_CURR_HOST_TX_BUFF_OFST)
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/* Current Host Transmit Buffer Address */
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#define EMAC_DMA_CURR_HOST_RX_BUFF_ADDR(base) (uint32_t)((base) + EMAC_DMA_CURR_HOST_RX_BUFF_OFST)
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/* Current Host Receive Buffer Address */
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#define EMAC_DMA_HW_FEATURE_ADDR(base) (uint32_t)((base) + EMAC_DMA_HW_FEATURE_OFST)
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/* HW Feature */
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/* Bus Mode */
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#define EMAC_DMA_MODE_OFST 0x1000
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#define EMAC_DMA_MODE_SWR_SET_MSK 0x00000001
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#define EMAC_DMA_MODE_SWR_GET(value) (((value)&0x00000001) >> 0)
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#define EMAC_DMA_MODE_FB_SET_MSK 0x00010000
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#define EMAC_DMA_MODE_RPBL_SET(value) (((value) << 17) & 0x007e0000)
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#define EMAC_DMA_MODE_PBL_SET(value) (((value) << 8) & 0x00003f00)
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#define EMAC_DMA_MODE_EIGHTXPBL_SET(value) (((value) << 24) & 0x01000000)
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#define EMAC_DMA_MODE_AAL_SET_MSK 0x02000000
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#define EMAC_DMA_MODE_USP_SET_MSK 0x00800000
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/* Receive Descriptor Address List */
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#define EMAC_DMA_RX_DESC_LIST_OFST 0x100c
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/* Transceive Descriptor Address List */
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#define EMAC_DMA_TX_DESC_LIST_OFST 0x1010
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/* Operation Mode */
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#define EMAC_DMAGRP_OPERATION_MODE_OFST 0x1018
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#define EMAC_DMAGRP_OPERATION_MODE_OSF_SET_MSK 0x00000004 /* Operate on Second Frame */
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#define EMAC_DMAGRP_OPERATION_MODE_TSF_SET_MSK 0x00200000 /* Transmit Store and Forward */
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#define EMAC_DMAGRP_OPERATION_MODE_RSF_SET_MSK 0x02000000 /* Receive Store and Forward */
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#define EMAC_DMAGRP_OPERATION_MODE_FTF_SET_MSK 0x00100000 /* Receive Store and Forward */
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#define EMAC_DMAGRP_OPERATION_MODE_ST_SET_MSK 0x00002000
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#define EMAC_DMAGRP_OPERATION_MODE_SR_SET_MSK 0x00000002
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#define EMAC_DMAGRP_OPERATION_MODE_DT_SET_MSK 0x04000000 /* Ignore frame errors */
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/* Interrupt Enable */
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#define EMAC_DMA_INT_EN_OFST 0x101C
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#define EMAC_DMA_INT_EN_NIE_SET_MSK 0x00010000
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#define EMAC_DMA_INT_EN_AIE_SET_MSK 0x00008000
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#define EMAC_DMA_INT_EN_ERE_SET_MSK 0x00004000
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#define EMAC_DMA_INT_EN_FBE_SET_MSK 0x00002000
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#define EMAC_DMA_INT_EN_ETE_SET_MSK 0x00000400
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#define EMAC_DMA_INT_EN_RWE_SET_MSK 0x00000200
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#define EMAC_DMA_INT_EN_RSE_SET_MSK 0x00000100
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#define EMAC_DMA_INT_EN_RUE_SET_MSK 0x00000080
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#define EMAC_DMA_INT_EN_RIE_SET_MSK 0x00000040
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#define EMAC_DMA_INT_EN_UNE_SET_MSK 0x00000020
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#define EMAC_DMA_INT_EN_OVE_SET_MSK 0x00000010
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#define EMAC_DMA_INT_EN_TJE_SET_MSK 0x00000008
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#define EMAC_DMA_INT_EN_TUE_SET_MSK 0x00000004
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#define EMAC_DMA_INT_EN_TSE_SET_MSK 0x00000002
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#define EMAC_DMA_INT_EN_TIE_SET_MSK 0x00000001
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/* Status */
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#define EMAC_DMAGRP_STATUS_OFST 0x1014
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#define EMAC_DMAGRP_STATUS_TS_SET_MSK 0x00700000
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#define EMAC_DMAGRP_STATUS_TS_E_SUSPTX 0x00600000
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#define EMAC_DMAGRP_STATUS_RS_SET_MSK 0x000e0000
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#define EMAC_DMAGRP_STATUS_RS_E_SUSPRX 0x00080000
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#define EMAC_DMAGRP_DEBUG_OFST 0x24
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#define EMAC_DMAGRP_DEBUG_TWCSTS 0x00400000
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#define EMAC_DMAGRP_DEBUG_RWCSTS 0x00000010
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#define EMAC_DMAGRP_DEBUG_RXFSTS_GET(value) (((value)&0x00000300) >> 8)
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/* AXI Bus Mode */
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#define EMAC_DMAGRP_AXI_BUS_MODE_OFST 0x1028
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#define EMAC_DMAGRP_AXI_BUS_MODE_BLEN16_SET_MSK 0x00000008
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/* AHB or AXI Status */
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#define EMAC_DMAGRP_AHB_OR_AXI_STATUS_OFST 0x102c
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/* MAC Configuration */
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#define EMAC_GMACGRP_MAC_CONFIGURATION_OFST 0x0000
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#define EMAC_GMACGRP_MAC_CONFIGURATION_IPC_SET_MSK 0x00000400
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#define EMAC_GMACGRP_MAC_CONFIGURATION_JD_SET_MSK 0x00400000 /* Jabber Disable */
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#define EMAC_GMACGRP_MAC_CONFIGURATION_PS_SET_MSK 0x00008000 /* Port Select = MII */
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#define EMAC_GMACGRP_MAC_CONFIGURATION_BE_SET_MSK 0x00200000 /* Frame Burst Enable */
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#define EMAC_GMACGRP_MAC_CONFIGURATION_WD_SET_MSK 0x00800000 /* Watchdog Disable */
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#define EMAC_GMACGRP_MAC_CONFIGURATION_DO_SET_MSK 0x00002000
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#define EMAC_GMACGRP_MAC_CONFIGURATION_TE_SET_MSK 0x00000008
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#define EMAC_GMACGRP_MAC_CONFIGURATION_RE_SET_MSK 0x00000004
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#define EMAC_GMACGRP_MAC_CONFIGURATION_TC_SET_MSK 0x01000000
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#define EMAC_GMACGRP_MAC_CONFIGURATION_DM_SET_MSK 0x00000800
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#define EMAC_GMACGRP_MAC_CONFIGURATION_FES_SET_MSK 0x00004000
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/* SGMII RGMII SMII Control Status */
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#define EMAC_GMACGRP_SGMII_RGMII_SMII_CONTROL_STATUS_OFST 0x00d8
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#define EMAC_GMAC_MII_CTL_STAT_LNKSTS_GET(value) (((value)&0x00000008) >> 3)
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#define EMAC_GMAC_MII_CTL_STAT_LNKSPEED_GET(value) (((value)&0x00000007) >> 1)
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#define EMAC_GMAC_MII_CTL_STAT_LNKMOD_GET(value) ((value)&0x00000001)
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/* Interrupt Mask */
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#define EMAC_GMAC_INT_MSK_OFST 0x003c
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#define EMAC_GMAC_INT_STAT_LPIIS_SET_MSK 0x00000400
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#define EMAC_GMAC_INT_STAT_TSIS_SET_MSK 0x00000200
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#define EMAC_GMAC_INT_STAT_RGSMIIIS_SET_MSK 0x00000001
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/* Interrupt Status (Gmac)*/
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#define EMAC_GMAC_INT_STAT_OFST 0x0038
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/* MAC Frame Filter */
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#define EMAC_GMACGRP_MAC_FRAME_FILTER_OFST 0x0004
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#define EMAC_GMACGRP_MAC_FRAME_FILTER_PR_SET_MSK 0x00000001
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/* MAC Address 0 High */
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#define EMAC_GMAC_MAC_ADDR0_HIGH_OFST 0x40
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#define EMAC_GMAC_MAC_ADDR_HIGH_OFST(n) (0x40 + 8 * (n))
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/* MAC Address 0 Low */
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#define EMAC_GMAC_MAC_ADDR0_LOW_OFST 0x44
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#define EMAC_GMAC_MAC_ADDR_LOW_OFST(n) (0x44 + 8 * (n))
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/* GMII Address */
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#define EMAC_GMAC_GMII_ADDR_OFST 0x10
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#define EMAC_GMAC_GMII_ADDR_PA_SET(value) (((value) << 11) & 0x0000f800)
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#define EMAC_GMAC_GMII_ADDR_GR_SET(value) (((value) << 6) & 0x000007c0)
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#define EMAC_GMAC_GMII_ADDR_GW_SET_MSK 0x00000002
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#define EMAC_GMAC_GMII_ADDR_GW_CLR_MSK 0xfffffffd
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#define EMAC_GMAC_GMII_ADDR_CR_SET(value) (((value) << 2) & 0x0000003c)
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#define EMAC_GMAC_GMII_ADDR_GB_SET(value) (((value) << 0) & 0x00000001)
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#define EMAC_GMAC_GMII_ADDR_CR_E_DIV102 0x4
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#define EMAC_GMAC_GMII_ADDR_GB_SET_MSK 0x00000001
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/* GMII Data */
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#define EMAC_GMAC_GMII_DATA_OFST 0x14
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/* Transmit Poll Demand */
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#define EMAC_DMA_TX_POLL_DEMAND_OFST 0x1004
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/* Receive Poll Demand */
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#define EMAC_DMA_RX_POLL_DEMAND_OFST 0x1008
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/* Current Host Transmit Descriptor */
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#define EMAC_DMA_CURR_HOST_TX_DESC_OFST 0x1048
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/* Current Host Receive Descriptor */
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#define EMAC_DMA_CURR_HOST_RX_DESC_OFST 0x104C
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/* Current Host Transmit Buffer Address */
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#define EMAC_DMA_CURR_HOST_TX_BUFF_OFST 0x1050
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/* Current Host Receive Buffer Address */
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#define EMAC_DMA_CURR_HOST_RX_BUFF_OFST 0x1054
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/* HW Feature */
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#define EMAC_DMA_HW_FEATURE_OFST 0x1058
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#define EMAC_DMA_HW_FEATURE_MIISEL 0x00000001 /* 10/100 Mbps support */
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#define EMAC_DMA_HW_FEATURE_GMIISEL 0x00000002 /* 1000 Mbps support */
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#define EMAC_DMA_HW_FEATURE_HDSEL 0x00000004 /* Half-Duplex support */
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#define EMAC_DMA_HW_FEATURE_RXTYP2COE 0x00040000 /* IP Checksum Offload (Type 2) in Rx */
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#define EMAC_DMA_HW_FEATURE_RXTYP1COE 0x00020000 /* IP Checksum Offload (Type 1) in Rx */
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#define EMAC_DMA_HW_FEATURE_TXOESEL 0x00010000 /* Checksum Offload in Tx */
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/*
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* DMA Descriptor Flag Definitions
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*/
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/*
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* DMA Rx Descriptor
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* -------------------------------------------------------------------------------------------
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* RDES0 | OWN(31) | Status [30:0] |
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* -------------------------------------------------------------------------------------------
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* RDES1 |CTRL(31)|Reserv[30:29]|Buff2ByteCt[28:16]|CTRL[15:14]
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* Reservr(13)|Buff1ByteCt[12:0]|
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* -------------------------------------------------------------------------------------------
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* RDES2 | Buffer1 Address [31:0] |
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* --------------------------------------------------------------------------------------------
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* RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0]
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* |
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* --------------------------------------------------------------------------------------------
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*/
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/* Bit definition of RDES0 register: DMA Rx descriptor status register */
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#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000)
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/*!< OWN bit: descriptor is owned by DMA engine */
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#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000)
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/*!< DA Filter Fail for the rx frame */
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#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000)
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/*!< Receive descriptor frame length */
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#define ETH_DMARXDESC_ES ((uint32_t)0x00008000)
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/*!< Error summary: OR of the following bits:
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* DE || OE || IPC || LC || RWT || RE || CE
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*/
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#define ETH_DMARXDESC_DE ((uint32_t)0x00004000)
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/*!< Descriptor error: no more descriptors for receive frame */
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#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000)
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/*!< SA Filter Fail for the received frame */
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#define ETH_DMARXDESC_LE ((uint32_t)0x00001000)
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/*!< Frame size not matching with length field */
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#define ETH_DMARXDESC_OE ((uint32_t)0x00000800)
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/*!< Overflow Error: Frame was damaged due to buffer overflow */
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#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400)
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/*!< VLAN Tag: received frame is a VLAN frame */
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#define ETH_DMARXDESC_FS ((uint32_t)0x00000200)
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/*!< First descriptor of the frame */
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#define ETH_DMARXDESC_LS ((uint32_t)0x00000100)
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/*!< Last descriptor of the frame */
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#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080)
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/*!< IPC Checksum Error: Rx Ipv4 header checksum error */
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#define ETH_DMARXDESC_LC ((uint32_t)0x00000040)
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/*!< Late collision occurred during reception */
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#define ETH_DMARXDESC_FT ((uint32_t)0x00000020)
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/*!< Frame type - Ethernet, otherwise 802.3 */
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#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010)
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/*!< Receive Watchdog Timeout: watchdog timer expired during reception */
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#define ETH_DMARXDESC_RE ((uint32_t)0x00000008)
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/*!< Receive error: error reported by MII interface */
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#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004)
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/*!< Dribble bit error: frame contains non int multiple of 8 bits */
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#define ETH_DMARXDESC_CE ((uint32_t)0x00000002)
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/*!< CRC error */
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#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001)
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/* !< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/
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* Rx Payload Checksum Error
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*/
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/* Bit definition of RDES1 register */
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#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
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#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
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#define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */
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#define ETH_DMARXDESC_RCH \
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((uint32_t)0x00004000) /*!< Second Address Chained \
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*/
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#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
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/*
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*DMA Tx Descriptor
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*-----------------------------------------------------------------------------------------------
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*TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] |
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*Reserved[19:17] | Status[16:0] |
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*-----------------------------------------------------------------------------------------------
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*TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1
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*ByteCount[12:0] |
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*-----------------------------------------------------------------------------------------------
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*TDES2 | Buffer1 Address [31:0]
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*|
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*-----------------------------------------------------------------------------------------------
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*TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0]
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*|
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*-----------------------------------------------------------------------------------------------
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*/
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/* Bit definition of TDES0 register: DMA Tx descriptor status register */
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#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000)
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/*!< OWN bit: descriptor is owned by DMA engine */
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#define ETH_DMATXDESC_IC ((uint32_t)0x40000000)
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/*!< Interrupt on Completion */
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#define ETH_DMATXDESC_LS ((uint32_t)0x20000000)
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/*!< Last Segment */
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#define ETH_DMATXDESC_FS ((uint32_t)0x10000000)
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/*!< First Segment */
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#define ETH_DMATXDESC_DC ((uint32_t)0x08000000)
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/*!< Disable CRC */
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#define ETH_DMATXDESC_DP ((uint32_t)0x04000000)
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/*!< Disable Padding */
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#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000)
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/*!< Transmit Time Stamp Enable */
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#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000)
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/*!< Checksum Insertion Control: 4 cases */
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#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000)
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/*!< Do Nothing: Checksum Engine is bypassed */
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#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000)
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/*!< IPV4 header Checksum Insertion */
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#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000)
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/*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
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#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000)
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/*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
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#define ETH_DMATXDESC_TER ((uint32_t)0x00200000)
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/*!< Transmit End of Ring */
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#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000)
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/*!< Second Address Chained */
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#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000)
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/*!< Tx Time Stamp Status */
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#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000)
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/*!< IP Header Error */
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#define ETH_DMATXDESC_ES ((uint32_t)0x00008000)
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/*!< Error summary: OR of the following bits: UE||ED||EC||LCO||NC||LCA||FF||JT
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*/
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#define ETH_DMATXDESC_JT ((uint32_t)0x00004000)
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/*!< Jabber Timeout */
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#define ETH_DMATXDESC_FF ((uint32_t)0x00002000)
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/*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
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#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000)
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/*!< Payload Checksum Error */
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#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800)
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/*!< Loss of Carrier: carrier lost during transmission */
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#define ETH_DMATXDESC_NC ((uint32_t)0x00000400)
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/*!< No Carrier: no carrier signal from the transceiver */
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#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200)
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/*!< Late Collision: transmission aborted due to collision */
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#define ETH_DMATXDESC_EC ((uint32_t)0x00000100)
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/*!< Excessive Collision: transmission aborted after 16 collisions */
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#define ETH_DMATXDESC_VF ((uint32_t)0x00000080)
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/*!< VLAN Frame */
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#define ETH_DMATXDESC_CC ((uint32_t)0x00000078)
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/*!< Collision Count */
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#define ETH_DMATXDESC_ED ((uint32_t)0x00000004)
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/*!< Excessive Deferral */
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#define ETH_DMATXDESC_UF ((uint32_t)0x00000002)
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/*!< Underflow Error: late data arrival from the memory */
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#define ETH_DMATXDESC_DB ((uint32_t)0x00000001)
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/*!< Deferred Bit */
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/* Bit definition of TDES1 register */
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#define ETH_DMATXDESC_TBS2 \
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((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size \
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*/
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#define ETH_DMATXDESC_TBS1 \
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((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size \
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*/
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/* Bit definition of TDES2 register */
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#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
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/* Bit definition of TDES3 register */
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#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
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static const uint32_t Rstmgr_Permodrst_Emac_Set_Msk[] = {RSTMGR_PERMODRST_EMAC0_SET_MSK,
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RSTMGR_PERMODRST_EMAC1_SET_MSK};
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static const uint32_t Sysmgr_Core_Emac_Phy_Intf_Sel_Set_Msk[] = {SYSMGR_EMAC0_PHY_INTF_SEL_SET_MSK,
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SYSMGR_EMAC1_PHY_INTF_SEL_SET_MSK};
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static const uint32_t Sysmgr_Fpgaintf_En_3_Emac_Set_Msk[] = {SYSMGR_FPGAINTF_MODULE_EMAC_0_SET_MSK,
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SYSMGR_FPGAINTF_MODULE_EMAC_1_SET_MSK};
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static const uint32_t Sysmgr_Emac_Phy_Intf_Sel_E_Rgmii[] = {SYSMGR_EMAC0_PHY_INTF_SEL_E_RGMII,
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SYSMGR_EMAC1_PHY_INTF_SEL_E_RGMII};
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#endif
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