479 lines
13 KiB
C
479 lines
13 KiB
C
/*
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* Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/counter.h>
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#include <hal/nrf_timer.h>
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#include <zephyr/sys/atomic.h>
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#define LOG_LEVEL CONFIG_COUNTER_LOG_LEVEL
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#define LOG_MODULE_NAME counter_timer
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#include <zephyr/logging/log.h>
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#include <zephyr/irq.h>
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LOG_MODULE_REGISTER(LOG_MODULE_NAME, LOG_LEVEL);
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#define TIMER_CLOCK 16000000
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#define CC_TO_ID(cc_num) (cc_num - 2)
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#define ID_TO_CC(idx) (nrf_timer_cc_channel_t)(idx + 2)
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#define TOP_CH NRF_TIMER_CC_CHANNEL0
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#define COUNTER_TOP_EVT NRF_TIMER_EVENT_COMPARE0
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#define COUNTER_TOP_INT_MASK NRF_TIMER_INT_COMPARE0_MASK
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#define COUNTER_OVERFLOW_SHORT NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK
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#define COUNTER_READ_CC NRF_TIMER_CC_CHANNEL1
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struct counter_nrfx_data {
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counter_top_callback_t top_cb;
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void *top_user_data;
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uint32_t guard_period;
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atomic_t cc_int_pending;
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};
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struct counter_nrfx_ch_data {
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counter_alarm_callback_t callback;
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void *user_data;
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};
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struct counter_nrfx_config {
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struct counter_config_info info;
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struct counter_nrfx_ch_data *ch_data;
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NRF_TIMER_Type *timer;
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LOG_INSTANCE_PTR_DECLARE(log);
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};
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struct counter_timer_config {
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nrf_timer_bit_width_t bit_width;
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nrf_timer_mode_t mode;
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nrf_timer_frequency_t freq;
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};
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static int start(const struct device *dev)
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{
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const struct counter_nrfx_config *config = dev->config;
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nrf_timer_task_trigger(config->timer, NRF_TIMER_TASK_START);
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return 0;
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}
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static int stop(const struct device *dev)
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{
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const struct counter_nrfx_config *config = dev->config;
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nrf_timer_task_trigger(config->timer, NRF_TIMER_TASK_SHUTDOWN);
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return 0;
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}
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static uint32_t get_top_value(const struct device *dev)
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{
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const struct counter_nrfx_config *config = dev->config;
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return nrf_timer_cc_get(config->timer, TOP_CH);
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}
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static uint32_t read(const struct device *dev)
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{
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const struct counter_nrfx_config *config = dev->config;
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NRF_TIMER_Type *timer = config->timer;
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nrf_timer_task_trigger(timer,
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nrf_timer_capture_task_get(COUNTER_READ_CC));
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return nrf_timer_cc_get(timer, COUNTER_READ_CC);
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}
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static int get_value(const struct device *dev, uint32_t *ticks)
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{
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*ticks = read(dev);
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return 0;
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}
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/* Return true if value equals 2^n - 1 */
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static inline bool is_bit_mask(uint32_t val)
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{
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return !(val & (val + 1));
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}
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static uint32_t ticks_add(uint32_t val1, uint32_t val2, uint32_t top)
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{
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uint32_t to_top;
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if (likely(is_bit_mask(top))) {
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return (val1 + val2) & top;
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}
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to_top = top - val1;
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return (val2 <= to_top) ? val1 + val2 : val2 - to_top;
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}
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static uint32_t ticks_sub(uint32_t val, uint32_t old, uint32_t top)
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{
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if (likely(is_bit_mask(top))) {
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return (val - old) & top;
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}
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/* if top is not 2^n-1 */
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return (val >= old) ? (val - old) : val + top + 1 - old;
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}
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static void set_cc_int_pending(const struct device *dev, uint8_t chan)
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{
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const struct counter_nrfx_config *config = dev->config;
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struct counter_nrfx_data *data = dev->data;
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atomic_or(&data->cc_int_pending, BIT(chan));
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NRFX_IRQ_PENDING_SET(NRFX_IRQ_NUMBER_GET(config->timer));
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}
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static int set_cc(const struct device *dev, uint8_t id, uint32_t val,
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uint32_t flags)
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{
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const struct counter_nrfx_config *config = dev->config;
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struct counter_nrfx_data *data = dev->data;
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__ASSERT_NO_MSG(data->guard_period < get_top_value(dev));
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bool absolute = flags & COUNTER_ALARM_CFG_ABSOLUTE;
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bool irq_on_late;
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NRF_TIMER_Type *reg = config->timer;
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uint8_t chan = ID_TO_CC(id);
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nrf_timer_event_t evt = nrf_timer_compare_event_get(chan);
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uint32_t top = get_top_value(dev);
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int err = 0;
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uint32_t prev_val;
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uint32_t now;
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uint32_t diff;
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uint32_t max_rel_val;
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__ASSERT(nrf_timer_int_enable_check(reg,
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nrf_timer_compare_int_get(chan)) == 0,
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"Expected that CC interrupt is disabled.");
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/* First take care of a risk of an event coming from CC being set to
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* next tick. Reconfigure CC to future (now tick is the furthest
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* future).
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*/
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now = read(dev);
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prev_val = nrf_timer_cc_get(reg, chan);
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nrf_timer_cc_set(reg, chan, now);
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nrf_timer_event_clear(reg, evt);
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if (absolute) {
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max_rel_val = top - data->guard_period;
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irq_on_late = flags & COUNTER_ALARM_CFG_EXPIRE_WHEN_LATE;
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} else {
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/* If relative value is smaller than half of the counter range
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* it is assumed that there is a risk of setting value too late
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* and late detection algorithm must be applied. When late
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* setting is detected, interrupt shall be triggered for
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* immediate expiration of the timer. Detection is performed
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* by limiting relative distance between CC and counter.
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*
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* Note that half of counter range is an arbitrary value.
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*/
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irq_on_late = val < (top / 2);
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/* limit max to detect short relative being set too late. */
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max_rel_val = irq_on_late ? top / 2 : top;
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val = ticks_add(now, val, top);
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}
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nrf_timer_cc_set(reg, chan, val);
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/* decrement value to detect also case when val == read(dev). Otherwise,
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* condition would need to include comparing diff against 0.
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*/
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diff = ticks_sub(val - 1, read(dev), top);
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if (diff > max_rel_val) {
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if (absolute) {
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err = -ETIME;
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}
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/* Interrupt is triggered always for relative alarm and
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* for absolute depending on the flag.
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*/
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if (irq_on_late) {
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set_cc_int_pending(dev, chan);
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} else {
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config->ch_data[id].callback = NULL;
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}
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} else {
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nrf_timer_int_enable(reg, nrf_timer_compare_int_get(chan));
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}
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return err;
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}
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static int set_alarm(const struct device *dev, uint8_t chan,
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const struct counter_alarm_cfg *alarm_cfg)
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{
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const struct counter_nrfx_config *nrfx_config = dev->config;
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struct counter_nrfx_ch_data *chdata = &nrfx_config->ch_data[chan];
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if (alarm_cfg->ticks > get_top_value(dev)) {
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return -EINVAL;
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}
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if (chdata->callback) {
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return -EBUSY;
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}
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chdata->callback = alarm_cfg->callback;
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chdata->user_data = alarm_cfg->user_data;
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return set_cc(dev, chan, alarm_cfg->ticks, alarm_cfg->flags);
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}
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static int cancel_alarm(const struct device *dev, uint8_t chan_id)
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{
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const struct counter_nrfx_config *config = dev->config;
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uint32_t int_mask = nrf_timer_compare_int_get(ID_TO_CC(chan_id));
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nrf_timer_int_disable(config->timer, int_mask);
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config->ch_data[chan_id].callback = NULL;
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return 0;
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}
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static int set_top_value(const struct device *dev,
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const struct counter_top_cfg *cfg)
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{
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const struct counter_nrfx_config *nrfx_config = dev->config;
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NRF_TIMER_Type *timer = nrfx_config->timer;
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struct counter_nrfx_data *data = dev->data;
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int err = 0;
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for (int i = 0; i < counter_get_num_of_channels(dev); i++) {
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/* Overflow can be changed only when all alarms are
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* disables.
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*/
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if (nrfx_config->ch_data[i].callback) {
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return -EBUSY;
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}
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}
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nrf_timer_int_disable(timer, COUNTER_TOP_INT_MASK);
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nrf_timer_cc_set(timer, TOP_CH, cfg->ticks);
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nrf_timer_shorts_enable(timer, COUNTER_OVERFLOW_SHORT);
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data->top_cb = cfg->callback;
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data->top_user_data = cfg->user_data;
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if (!(cfg->flags & COUNTER_TOP_CFG_DONT_RESET)) {
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nrf_timer_task_trigger(timer, NRF_TIMER_TASK_CLEAR);
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} else if (read(dev) >= cfg->ticks) {
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err = -ETIME;
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if (cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE) {
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nrf_timer_task_trigger(timer, NRF_TIMER_TASK_CLEAR);
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}
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}
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if (cfg->callback) {
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nrf_timer_int_enable(timer, COUNTER_TOP_INT_MASK);
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}
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return err;
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}
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static uint32_t get_pending_int(const struct device *dev)
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{
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return 0;
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}
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static int init_timer(const struct device *dev,
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const struct counter_timer_config *config)
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{
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const struct counter_nrfx_config *nrfx_config = dev->config;
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NRF_TIMER_Type *reg = nrfx_config->timer;
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nrf_timer_bit_width_set(reg, config->bit_width);
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nrf_timer_mode_set(reg, config->mode);
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nrf_timer_prescaler_set(reg, config->freq);
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nrf_timer_cc_set(reg, TOP_CH, counter_get_max_top_value(dev));
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NRFX_IRQ_ENABLE(NRFX_IRQ_NUMBER_GET(reg));
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return 0;
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}
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static uint32_t get_guard_period(const struct device *dev, uint32_t flags)
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{
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struct counter_nrfx_data *data = dev->data;
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return data->guard_period;
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}
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static int set_guard_period(const struct device *dev, uint32_t guard,
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uint32_t flags)
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{
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struct counter_nrfx_data *data = dev->data;
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__ASSERT_NO_MSG(guard < get_top_value(dev));
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data->guard_period = guard;
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return 0;
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}
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static void top_irq_handle(const struct device *dev)
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{
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const struct counter_nrfx_config *config = dev->config;
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struct counter_nrfx_data *data = dev->data;
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NRF_TIMER_Type *reg = config->timer;
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counter_top_callback_t cb = data->top_cb;
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if (nrf_timer_event_check(reg, COUNTER_TOP_EVT) &&
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nrf_timer_int_enable_check(reg, COUNTER_TOP_INT_MASK)) {
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nrf_timer_event_clear(reg, COUNTER_TOP_EVT);
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__ASSERT(cb != NULL, "top event enabled - expecting callback");
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cb(dev, data->top_user_data);
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}
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}
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static void alarm_irq_handle(const struct device *dev, uint32_t id)
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{
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const struct counter_nrfx_config *config = dev->config;
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struct counter_nrfx_data *data = dev->data;
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uint32_t cc = ID_TO_CC(id);
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NRF_TIMER_Type *reg = config->timer;
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uint32_t int_mask = nrf_timer_compare_int_get(cc);
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nrf_timer_event_t evt = nrf_timer_compare_event_get(cc);
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bool hw_irq_pending = nrf_timer_event_check(reg, evt) &&
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nrf_timer_int_enable_check(reg, int_mask);
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bool sw_irq_pending = data->cc_int_pending & BIT(cc);
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if (hw_irq_pending || sw_irq_pending) {
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struct counter_nrfx_ch_data *chdata;
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counter_alarm_callback_t cb;
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nrf_timer_event_clear(reg, evt);
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atomic_and(&data->cc_int_pending, ~BIT(cc));
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nrf_timer_int_disable(reg, int_mask);
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chdata = &config->ch_data[id];
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cb = chdata->callback;
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chdata->callback = NULL;
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if (cb) {
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uint32_t cc_val = nrf_timer_cc_get(reg, cc);
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cb(dev, id, cc_val, chdata->user_data);
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}
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}
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}
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static void irq_handler(const struct device *dev)
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{
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top_irq_handle(dev);
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for (uint32_t i = 0; i < counter_get_num_of_channels(dev); i++) {
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alarm_irq_handle(dev, i);
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}
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}
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static const struct counter_driver_api counter_nrfx_driver_api = {
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.start = start,
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.stop = stop,
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.get_value = get_value,
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.set_alarm = set_alarm,
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.cancel_alarm = cancel_alarm,
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.set_top_value = set_top_value,
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.get_pending_int = get_pending_int,
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.get_top_value = get_top_value,
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.get_guard_period = get_guard_period,
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.set_guard_period = set_guard_period,
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};
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/*
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* Device instantiation is done with node labels due to HAL API
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* requirements. In particular, TIMERx_MAX_SIZE values from HALs
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* are indexed by peripheral number, so DT_INST APIs won't work.
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*/
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#define TIMER(idx) DT_NODELABEL(timer##idx)
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#define TIMER_PROP(idx, prop) DT_PROP(TIMER(idx), prop)
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#define TIMER_IRQ_CONNECT(idx) \
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COND_CODE_1(CONFIG_COUNTER_TIMER##idx##_ZLI, \
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(IRQ_DIRECT_CONNECT(DT_IRQN(TIMER(idx)), \
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DT_IRQ(TIMER(idx), priority), \
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counter_timer##idx##_isr_wrapper, \
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IRQ_ZERO_LATENCY)), \
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(IRQ_CONNECT(DT_IRQN(TIMER(idx)), DT_IRQ(TIMER(idx), priority),\
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irq_handler, DEVICE_DT_GET(TIMER(idx)), 0)) \
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)
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#define COUNTER_NRFX_TIMER_DEVICE(idx) \
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BUILD_ASSERT(TIMER_PROP(idx, prescaler) <= \
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TIMER_PRESCALER_PRESCALER_Msk, \
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"TIMER prescaler out of range"); \
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COND_CODE_1(CONFIG_COUNTER_TIMER##idx##_ZLI, ( \
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ISR_DIRECT_DECLARE(counter_timer##idx##_isr_wrapper) \
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{ \
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irq_handler(DEVICE_DT_GET(TIMER(idx))); \
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/* No rescheduling, it shall not access zephyr primitives. */ \
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return 0; \
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}), ()) \
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static int counter_##idx##_init(const struct device *dev) \
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{ \
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TIMER_IRQ_CONNECT(idx); \
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static const struct counter_timer_config config = { \
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.freq = TIMER_PROP(idx, prescaler), \
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.mode = NRF_TIMER_MODE_TIMER, \
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.bit_width = (TIMER##idx##_MAX_SIZE == 32) ? \
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NRF_TIMER_BIT_WIDTH_32 : \
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NRF_TIMER_BIT_WIDTH_16, \
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}; \
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return init_timer(dev, &config); \
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} \
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static struct counter_nrfx_data counter_##idx##_data; \
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static struct counter_nrfx_ch_data \
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counter##idx##_ch_data[CC_TO_ID(TIMER##idx##_CC_NUM)]; \
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LOG_INSTANCE_REGISTER(LOG_MODULE_NAME, idx, CONFIG_COUNTER_LOG_LEVEL); \
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static const struct counter_nrfx_config nrfx_counter_##idx##_config = {\
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.info = { \
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.max_top_value = (TIMER##idx##_MAX_SIZE == 32) ? \
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0xffffffff : 0x0000ffff, \
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.freq = TIMER_CLOCK / \
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(1 << TIMER_PROP(idx, prescaler)), \
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.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
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.channels = CC_TO_ID(TIMER##idx##_CC_NUM), \
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}, \
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.ch_data = counter##idx##_ch_data, \
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.timer = (NRF_TIMER_Type *)DT_REG_ADDR(TIMER(idx)), \
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LOG_INSTANCE_PTR_INIT(log, LOG_MODULE_NAME, idx) \
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}; \
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DEVICE_DT_DEFINE(TIMER(idx), \
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counter_##idx##_init, \
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NULL, \
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&counter_##idx##_data, \
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&nrfx_counter_##idx##_config.info, \
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PRE_KERNEL_1, CONFIG_COUNTER_INIT_PRIORITY, \
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&counter_nrfx_driver_api)
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#ifdef CONFIG_COUNTER_TIMER0
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COUNTER_NRFX_TIMER_DEVICE(0);
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#endif
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#ifdef CONFIG_COUNTER_TIMER1
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COUNTER_NRFX_TIMER_DEVICE(1);
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#endif
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#ifdef CONFIG_COUNTER_TIMER2
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COUNTER_NRFX_TIMER_DEVICE(2);
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#endif
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#ifdef CONFIG_COUNTER_TIMER3
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COUNTER_NRFX_TIMER_DEVICE(3);
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#endif
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#ifdef CONFIG_COUNTER_TIMER4
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COUNTER_NRFX_TIMER_DEVICE(4);
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#endif
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