56 lines
1.6 KiB
C
56 lines
1.6 KiB
C
/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <irq.h>
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/*
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* In RISC-V there is no conventional way to handle CPU power save.
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* Each RISC-V SOC handles it in its own way.
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* Hence, by default, k_cpu_idle and k_cpu_atomic_idle functions just
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* unlock interrupts and return to the caller, without issuing any CPU power
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* saving instruction.
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*
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* Nonetheless, define the default k_cpu_idle and k_cpu_atomic_idle
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* functions as weak functions, so that they can be replaced at the SOC-level.
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*/
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/**
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*
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* @brief Power save idle routine
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*
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* This function will be called by the kernel idle loop or possibly within
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* an implementation of _sys_power_save_idle in the kernel when the
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* '_sys_power_save_flag' variable is non-zero.
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*
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* @return N/A
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*/
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void __weak k_cpu_idle(void)
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{
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irq_unlock(SOC_MSTATUS_IEN);
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}
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/**
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*
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* @brief Atomically re-enable interrupts and enter low power mode
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*
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* INTERNAL
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* The requirements for k_cpu_atomic_idle() are as follows:
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* 1) The enablement of interrupts and entering a low-power mode needs to be
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* atomic, i.e. there should be no period of time where interrupts are
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* enabled before the processor enters a low-power mode. See the comments
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* in k_lifo_get(), for example, of the race condition that
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* occurs if this requirement is not met.
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*
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* 2) After waking up from the low-power mode, the interrupt lockout state
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* must be restored as indicated in the 'imask' input parameter.
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*
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* @return N/A
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*/
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void __weak k_cpu_atomic_idle(unsigned int key)
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{
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irq_unlock(key);
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}
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