223 lines
6.2 KiB
C
223 lines
6.2 KiB
C
/* nano_private.h - private nanokernel definitions (ARM) */
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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DESCRIPTION
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This file contains private nanokernel structures definitions and various other
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definitions for the ARM Cortex-M3 processor architecture.
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This file is also included by assembly language files which must #define
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_ASMLANGUAGE before including this header file. Note that nanokernel assembly
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source files obtains structure offset values via "absolute symbols" in the
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offsets.o module.
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*/
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#ifndef _NANO_PRIVATE_H
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#define _NANO_PRIVATE_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <toolchain.h>
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#include <sections.h>
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#include <arch/cpu.h>
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#ifndef _ASMLANGUAGE
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#include <../../../kernel/nanokernel/include/nano_internal.h>
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#include <stdint.h>
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#include <misc/dlist.h>
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#endif
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#ifndef _ASMLANGUAGE
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struct coop {
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/*
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* Unused for Cortex-M, which automatically saves the neccesary
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*registers
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* in its exception stack frame.
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*
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* For Cortex-A, this may be:
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*
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* uint32_t a1; // r0
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* uint32_t a2; // r1
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* uint32_t a3; // r2
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* uint32_t a4; // r3
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* uint32_t ip; // r12
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* uint32_t lr; // r14
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* uint32_t pc; // r15
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* uint32_t xpsr;
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*/
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};
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typedef struct __esf tESF;
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struct preempt {
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uint32_t v1; /* r4 */
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uint32_t v2; /* r5 */
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uint32_t v3; /* r6 */
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uint32_t v4; /* r7 */
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uint32_t v5; /* r8 */
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uint32_t v6; /* r9 */
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uint32_t v7; /* r10 */
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uint32_t v8; /* r11 */
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uint32_t psp; /* r13 */
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};
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typedef struct preempt tPreempt;
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#endif /* _ASMLANGUAGE */
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/* Bitmask definitions for the tCCS->flags bit field */
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#define FIBER 0x000
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#define TASK 0x001 /* 1 = task context, 0 = fiber context */
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#define INT_ACTIVE 0x002 /* 1 = context is executing interrupt handler */
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#define EXC_ACTIVE 0x004 /* 1 = context is executing exception handler */
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#define USE_FP 0x010 /* 1 = context uses floating point unit */
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#define PREEMPTIBLE \
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0x020 /* 1 = preemptible context \
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* NOTE: the value must be < 0x100 to be able to \
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* use a small thumb instr with immediate \
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* when loading PREEMPTIBLE in a GPR \
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*/
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#define ESSENTIAL 0x200 /* 1 = system context that must not abort */
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#define NO_METRICS 0x400 /* 1 = _Swap() not to update task metrics */
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/* stacks */
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#define STACK_GROWS_DOWN 0
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#define STACK_GROWS_UP 1
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#define STACK_ROUND_UP(x) ROUND_UP(x, STACK_ALIGN_SIZE)
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#define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN_SIZE)
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#ifdef CONFIG_CPU_CORTEX_M
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#include <CortexM/stack.h>
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#include <CortexM/exc.h>
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#endif
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#ifndef _ASMLANGUAGE
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struct ccs {
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struct ccs *link; /* singly-linked list in _nanokernel.fibers */
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uint32_t flags;
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uint32_t basepri;
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int prio;
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#ifdef CONFIG_CONTEXT_CUSTOM_DATA
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void *custom_data; /* available for custom use */
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#endif
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struct coop coopReg;
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struct preempt preempReg;
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#if defined(CONFIG_CONTEXT_MONITOR)
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struct ccs *next_context; /* next item in list of ALL fiber+tasks */
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#endif
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#ifdef CONFIG_NANO_TIMEOUTS
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struct _nano_timeout nano_timeout;
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#endif
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};
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struct s_NANO {
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tCCS *fiber; /* singly linked list of runnable fiber contexts */
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tCCS *task; /* pointer to runnable task context */
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tCCS *current; /* currently scheduled context (fiber or task) */
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int flags; /* tCCS->flags of 'current' context */
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#if defined(CONFIG_CONTEXT_MONITOR)
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tCCS *contexts; /* singly linked list of ALL fiber+tasks */
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#endif
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#ifdef CONFIG_FP_SHARING
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tCCS *current_fp; /* context (fiber or task) that owns the FP regs */
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#endif /* CONFIG_FP_SHARING */
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#ifdef CONFIG_ADVANCED_POWER_MANAGEMENT
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int32_t idle; /* Number of ticks for kernel idling */
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#endif /* CONFIG_ADVANCED_POWER_MANAGEMENT */
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#ifdef CONFIG_NANO_TIMEOUTS
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sys_dlist_t timeout_q;
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#endif
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};
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typedef struct s_NANO tNANO;
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extern tNANO _nanokernel;
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#endif /* _ASMLANGUAGE */
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#ifndef _ASMLANGUAGE
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extern void _FaultInit(void);
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extern void _CpuIdleInit(void);
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static ALWAYS_INLINE void nanoArchInit(void)
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{
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_nanokernel.flags = FIBER;
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_InterruptStackSetup();
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_ExcSetup();
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_FaultInit();
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_CpuIdleInit();
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}
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/**
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*
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* @brief Set the return value for the specified fiber (inline)
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*
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* The register used to store the return value from a function call invocation
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* to <value>. It is assumed that the specified <fiber> is pending, and thus
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* the fiber's context is stored in its tCCS structure.
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*
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* @return N/A
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*
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* \NOMANUAL
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*/
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static ALWAYS_INLINE void fiberRtnValueSet(
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tCCS *fiber, /* pointer to fiber */
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unsigned int value /* value to set as return value */
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)
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{
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tESF *pEsf = (void *)fiber->preempReg.psp;
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pEsf->a1 = value;
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}
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extern void nano_cpu_atomic_idle(unsigned int);
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#define _IS_IN_ISR() _IsInIsr()
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extern void _IntLibInit(void);
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _NANO_PRIVATE_H */
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