195 lines
4.4 KiB
C
195 lines
4.4 KiB
C
/*
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* Copyright (c) 2018 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef INTERRUPT_UTIL_H_
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#define INTERRUPT_UTIL_H_
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#define MS_TO_US(ms) (ms * USEC_PER_MSEC)
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#if defined(CONFIG_CPU_CORTEX_M)
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#include <arch/arm/aarch32/cortex_m/cmsis.h>
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static inline uint32_t get_available_nvic_line(uint32_t initial_offset)
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{
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int i;
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for (i = initial_offset - 1; i >= 0; i--) {
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if (NVIC_GetEnableIRQ(i) == 0) {
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/*
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* Interrupts configured statically with IRQ_CONNECT(.)
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* are automatically enabled. NVIC_GetEnableIRQ()
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* returning false, here, implies that the IRQ line is
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* either not implemented or it is not enabled, thus,
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* currently not in use by Zephyr.
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*/
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/* Set the NVIC line to pending. */
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NVIC_SetPendingIRQ(i);
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if (NVIC_GetPendingIRQ(i)) {
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/*
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* If the NVIC line is pending, it is
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* guaranteed that it is implemented; clear the
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* line.
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*/
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NVIC_ClearPendingIRQ(i);
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if (!NVIC_GetPendingIRQ(i)) {
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/*
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* If the NVIC line can be successfully
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* un-pended, it is guaranteed that it
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* can be used for software interrupt
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* triggering. Return the NVIC line
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* number.
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*/
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break;
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}
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}
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}
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}
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zassert_true(i >= 0, "No available IRQ line\n");
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return i;
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}
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static inline void trigger_irq(int irq)
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{
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printk("Triggering irq : %d\n", irq);
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#if defined(CONFIG_SOC_TI_LM3S6965_QEMU) || defined(CONFIG_CPU_CORTEX_M0) \
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|| defined(CONFIG_CPU_CORTEX_M0PLUS) || defined(CONFIG_CPU_CORTEX_M1)\
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|| defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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/* QEMU does not simulate the STIR register: this is a workaround */
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NVIC_SetPendingIRQ(irq);
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#else
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NVIC->STIR = irq;
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#endif
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}
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#elif defined(CONFIG_GIC)
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#include <drivers/interrupt_controller/gic.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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static inline void trigger_irq(int irq)
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{
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printk("Triggering irq : %d\n", irq);
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/* Ensure that the specified IRQ number is a valid SGI interrupt ID */
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zassert_true(irq <= 15, "%u is not a valid SGI interrupt ID", irq);
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/*
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* Generate a software generated interrupt and forward it to the
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* requesting CPU.
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*/
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#if CONFIG_GIC_VER <= 2
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sys_write32(GICD_SGIR_TGTFILT_REQONLY | GICD_SGIR_SGIINTID(irq),
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GICD_SGIR);
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#else
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gic_raise_sgi(irq, GET_MPIDR(), BIT(MPIDR_TO_CORE(GET_MPIDR())));
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#endif
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}
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#elif defined(CONFIG_ARC)
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static inline void trigger_irq(int irq)
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{
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printk("Triggering irq : %d\n", irq);
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z_arc_v2_aux_reg_write(_ARC_V2_AUX_IRQ_HINT, irq);
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}
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#elif defined(CONFIG_X86)
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#ifdef CONFIG_X2APIC
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#include <drivers/interrupt_controller/loapic.h>
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#define VECTOR_MASK 0xFF
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#else
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#include <sys/arch_interface.h>
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#define LOAPIC_ICR_IPI_TEST 0x00004000U
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#endif
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#define TRIGGER_IRQ_INT(vector) __asm__ volatile("int %0" : : "i" (vector) : "memory")
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/*
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* We can emulate the interrupt by sending the IPI to
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* core itself by the LOAPIC for x86 platform.
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*
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* In APIC mode, Write LOAPIC's ICR to trigger IPI,
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* the LOAPIC_ICR_IPI_TEST 0x00004000U means:
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* Delivery Mode: Fixed
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* Destination Mode: Physical
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* Level: Assert
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* Trigger Mode: Edge
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* Destination Shorthand: No Shorthand
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* Destination: depends on cpu_id
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*
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* In X2APIC mode, this no longer works. We emulate the
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* interrupt by writing the IA32_X2APIC_SELF_IPI MSR
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* to send IPI to the core itself via LOAPIC also.
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* According to SDM vol.3 chapter 10.12.11, the bit[7:0]
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* for setting the vector is only needed.
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*/
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static inline void trigger_irq(int vector)
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{
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#ifdef CONFIG_X2APIC
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x86_write_x2apic(LOAPIC_SELF_IPI, ((VECTOR_MASK & vector)));
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#else
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#ifdef CONFIG_SMP
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int cpu_id = arch_curr_cpu()->id;
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#else
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int cpu_id = 0;
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#endif
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z_loapic_ipi(cpu_id, LOAPIC_ICR_IPI_TEST, vector);
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#endif /* CONFIG_X2APIC */
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}
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#elif defined(CONFIG_ARCH_POSIX)
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#include "irq_ctrl.h"
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static inline void trigger_irq(int irq)
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{
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hw_irq_ctrl_raise_im_from_sw(irq);
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}
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#elif defined(CONFIG_RISCV)
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static inline void trigger_irq(int irq)
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{
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uint32_t mip;
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__asm__ volatile ("csrrs %0, mip, %1\n"
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: "=r" (mip)
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: "r" (1 << irq));
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}
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#elif defined(CONFIG_XTENSA)
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static inline void trigger_irq(int irq)
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{
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z_xt_set_intset(BIT((unsigned int)irq));
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}
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#elif defined(CONFIG_SPARC)
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extern void z_sparc_enter_irq(int);
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static inline void trigger_irq(int irq)
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{
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z_sparc_enter_irq(irq);
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}
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#elif defined(CONFIG_MIPS)
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extern void z_mips_enter_irq(int);
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static inline void trigger_irq(int irq)
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{
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z_mips_enter_irq(irq);
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}
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#else
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/* So far, Nios II does not support this */
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#define NO_TRIGGER_FROM_SW
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#endif
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#endif /* INTERRUPT_UTIL_H_ */
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