345 lines
8.0 KiB
C
345 lines
8.0 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <device.h>
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#include <init.h>
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#include <flash.h>
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#include <misc/util.h>
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#include "qm_flash.h"
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#include "qm_soc_regs.h"
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struct soc_flash_data {
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#ifdef CONFIG_SOC_FLASH_QMSI_API_REENTRANCY
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struct k_sem sem;
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#endif
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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u32_t device_power_state;
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qm_flash_context_t saved_ctx[QM_FLASH_NUM];
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#endif
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};
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#define FLASH_HAS_CONTEXT_DATA \
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(CONFIG_SOC_FLASH_QMSI_API_REENTRANCY || CONFIG_DEVICE_POWER_MANAGEMENT)
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#if FLASH_HAS_CONTEXT_DATA
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static struct soc_flash_data soc_flash_context;
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#define FLASH_CONTEXT (&soc_flash_context)
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#else
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#define FLASH_CONTEXT (NULL)
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#endif /* FLASH_HAS_CONTEXT_DATA */
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#ifdef CONFIG_SOC_FLASH_QMSI_API_REENTRANCY
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#define RP_GET(dev) (&((struct soc_flash_data *)(dev->driver_data))->sem)
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#else
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#define RP_GET(dev) (NULL)
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#endif
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static inline bool is_aligned_32(u32_t data)
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{
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return (data & 0x3) ? false : true;
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}
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static qm_flash_region_t flash_region(u32_t addr)
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{
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if ((addr >= QM_FLASH_REGION_SYS_0_BASE) && (addr <
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(QM_FLASH_REGION_SYS_0_BASE + CONFIG_SOC_FLASH_QMSI_SYS_SIZE))) {
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return QM_FLASH_REGION_SYS;
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}
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#if defined(CONFIG_SOC_QUARK_D2000)
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if ((addr >= QM_FLASH_REGION_DATA_0_BASE) &&
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(addr < (QM_FLASH_REGION_DATA_0_BASE +
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QM_FLASH_REGION_DATA_0_SIZE))) {
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return QM_FLASH_REGION_DATA;
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}
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#endif
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/* invalid address */
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return QM_FLASH_REGION_NUM;
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}
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static u32_t get_page_num(u32_t addr)
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{
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switch (flash_region(addr)) {
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case QM_FLASH_REGION_SYS:
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return (addr - QM_FLASH_REGION_SYS_0_BASE) >>
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QM_FLASH_PAGE_SIZE_BITS;
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#if defined(CONFIG_SOC_QUARK_D2000)
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case QM_FLASH_REGION_DATA:
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return (addr - QM_FLASH_REGION_DATA_0_BASE) >>
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QM_FLASH_PAGE_SIZE_BITS;
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#endif
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default:
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/* invalid address */
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return 0xffffffff;
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}
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}
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static int flash_qmsi_read(struct device *dev, off_t addr,
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void *data, size_t len)
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{
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ARG_UNUSED(dev);
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if ((!is_aligned_32(len)) || (!is_aligned_32(addr))) {
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return -EINVAL;
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}
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if (flash_region(addr) == QM_FLASH_REGION_NUM) {
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/* starting address is not within flash */
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return -EIO;
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}
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if (flash_region(addr + len - 4) == QM_FLASH_REGION_NUM) {
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/* data area is not within flash */
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return -EIO;
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}
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for (u32_t i = 0; i < (len >> 2); i++) {
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UNALIGNED_PUT(sys_read32(addr + (i << 2)),
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(u32_t *)data + i);
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}
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return 0;
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}
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static int flash_qmsi_write(struct device *dev, off_t addr,
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const void *data, size_t len)
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{
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qm_flash_t flash = QM_FLASH_0;
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qm_flash_region_t reg;
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u32_t data_word = 0, offset = 0, f_addr = 0;
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if ((!is_aligned_32(len)) || (!is_aligned_32(addr))) {
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return -EINVAL;
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}
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reg = flash_region(addr);
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if (reg == QM_FLASH_REGION_NUM) {
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return -EIO;
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}
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if (flash_region(addr + len - 4) == QM_FLASH_REGION_NUM) {
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return -EIO;
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}
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for (u32_t i = 0; i < (len >> 2); i++) {
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data_word = UNALIGNED_GET((u32_t *)data + i);
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reg = flash_region(addr + (i << 2));
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f_addr = addr + (i << 2);
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switch (reg) {
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case QM_FLASH_REGION_SYS:
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offset = f_addr - QM_FLASH_REGION_SYS_0_BASE;
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break;
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#if defined(CONFIG_SOC_QUARK_D2000)
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case QM_FLASH_REGION_DATA:
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offset = f_addr - QM_FLASH_REGION_DATA_0_BASE;
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break;
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#endif
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default:
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return -EIO;
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}
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#if defined(CONFIG_SOC_QUARK_SE_C1000) || defined(CONFIG_SOC_QUARK_SE_C1000_SS)
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if (offset >= (CONFIG_SOC_FLASH_QMSI_SYS_SIZE >> 1)) {
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flash = QM_FLASH_1;
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offset -= CONFIG_SOC_FLASH_QMSI_SYS_SIZE >> 1;
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}
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#endif
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if (IS_ENABLED(CONFIG_SOC_FLASH_QMSI_API_REENTRANCY)) {
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k_sem_take(RP_GET(dev), K_FOREVER);
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}
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qm_flash_word_write(flash, reg, offset, data_word);
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if (IS_ENABLED(CONFIG_SOC_FLASH_QMSI_API_REENTRANCY)) {
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k_sem_give(RP_GET(dev));
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}
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}
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return 0;
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}
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static int flash_qmsi_erase(struct device *dev, off_t addr, size_t size)
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{
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qm_flash_t flash = QM_FLASH_0;
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qm_flash_region_t reg;
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u32_t page = 0;
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/* starting address needs to be a 2KB aligned address */
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if (addr & QM_FLASH_ADDRESS_MASK) {
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return -EINVAL;
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}
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/* size needs to be multiple of 2KB */
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if (size & QM_FLASH_ADDRESS_MASK) {
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return -EINVAL;
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}
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reg = flash_region(addr);
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if (reg == QM_FLASH_REGION_NUM) {
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return -EIO;
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}
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if (flash_region(addr + size - (QM_FLASH_PAGE_SIZE_DWORDS << 2)) ==
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QM_FLASH_REGION_NUM) {
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return -EIO;
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}
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for (u32_t i = 0; i < (size >> QM_FLASH_PAGE_SIZE_BITS); i++) {
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page = get_page_num(addr) + i;
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#if defined(CONFIG_SOC_QUARK_SE_C1000) || defined(CONFIG_SOC_QUARK_SE_C1000_SS)
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if (page >= (CONFIG_SOC_FLASH_QMSI_SYS_SIZE >>
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(QM_FLASH_PAGE_SIZE_BITS + 1))) {
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flash = QM_FLASH_1;
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page -= (CONFIG_SOC_FLASH_QMSI_SYS_SIZE >>
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(QM_FLASH_PAGE_SIZE_BITS + 1));
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}
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#endif
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if (IS_ENABLED(CONFIG_SOC_FLASH_QMSI_API_REENTRANCY)) {
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k_sem_take(RP_GET(dev), K_FOREVER);
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}
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qm_flash_page_erase(flash, reg, page);
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if (IS_ENABLED(CONFIG_SOC_FLASH_QMSI_API_REENTRANCY)) {
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k_sem_give(RP_GET(dev));
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}
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}
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return 0;
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}
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static int flash_qmsi_write_protection(struct device *dev, bool enable)
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{
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qm_flash_config_t qm_cfg;
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qm_cfg.us_count = CONFIG_SOC_FLASH_QMSI_CLK_COUNT_US;
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qm_cfg.wait_states = CONFIG_SOC_FLASH_QMSI_WAIT_STATES;
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if (enable) {
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qm_cfg.write_disable = QM_FLASH_WRITE_DISABLE;
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} else {
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qm_cfg.write_disable = QM_FLASH_WRITE_ENABLE;
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}
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if (IS_ENABLED(CONFIG_SOC_FLASH_QMSI_API_REENTRANCY)) {
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k_sem_take(RP_GET(dev), K_FOREVER);
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}
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qm_flash_set_config(QM_FLASH_0, &qm_cfg);
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#if defined(CONFIG_SOC_QUARK_SE_C1000) || defined(CONFIG_SOC_QUARK_SE_C1000_SS)
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qm_flash_set_config(QM_FLASH_1, &qm_cfg);
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#endif
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if (IS_ENABLED(CONFIG_SOC_FLASH_QMSI_API_REENTRANCY)) {
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k_sem_give(RP_GET(dev));
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}
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return 0;
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}
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static const struct flash_driver_api flash_qmsi_api = {
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.read = flash_qmsi_read,
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.write = flash_qmsi_write,
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.erase = flash_qmsi_erase,
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.write_protection = flash_qmsi_write_protection,
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.write_block_size = 4,
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};
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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static void flash_qmsi_set_power_state(struct device *dev, u32_t power_state)
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{
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struct soc_flash_data *ctx = dev->driver_data;
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ctx->device_power_state = power_state;
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}
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static u32_t flash_qmsi_get_power_state(struct device *dev)
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{
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struct soc_flash_data *ctx = dev->driver_data;
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return ctx->device_power_state;
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}
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static int flash_qmsi_suspend_device(struct device *dev)
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{
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struct soc_flash_data *ctx = dev->driver_data;
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qm_flash_t i;
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for (i = QM_FLASH_0; i < QM_FLASH_NUM; i++) {
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qm_flash_save_context(i, &ctx->saved_ctx[i]);
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}
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flash_qmsi_set_power_state(dev, DEVICE_PM_SUSPEND_STATE);
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return 0;
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}
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static int flash_qmsi_resume_device(struct device *dev)
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{
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struct soc_flash_data *ctx = dev->driver_data;
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qm_flash_t i;
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for (i = QM_FLASH_0; i < QM_FLASH_NUM; i++) {
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qm_flash_restore_context(i, &ctx->saved_ctx[i]);
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}
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flash_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
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return 0;
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}
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static int flash_qmsi_device_ctrl(struct device *dev, u32_t ctrl_command,
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void *context)
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{
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if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
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if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
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return flash_qmsi_suspend_device(dev);
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} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
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return flash_qmsi_resume_device(dev);
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}
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} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
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*((u32_t *)context) = flash_qmsi_get_power_state(dev);
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}
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return 0;
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}
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#else
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#define flash_qmsi_set_power_state(...)
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#endif
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static int quark_flash_init(struct device *dev)
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{
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qm_flash_config_t qm_cfg;
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qm_cfg.us_count = CONFIG_SOC_FLASH_QMSI_CLK_COUNT_US;
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qm_cfg.wait_states = CONFIG_SOC_FLASH_QMSI_WAIT_STATES;
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qm_cfg.write_disable = QM_FLASH_WRITE_ENABLE;
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qm_flash_set_config(QM_FLASH_0, &qm_cfg);
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#if defined(CONFIG_SOC_QUARK_SE_C1000) || defined(CONFIG_SOC_QUARK_SE_C1000_SS)
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qm_flash_set_config(QM_FLASH_1, &qm_cfg);
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#endif
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if (IS_ENABLED(CONFIG_SOC_FLASH_QMSI_API_REENTRANCY)) {
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k_sem_init(RP_GET(dev), 1, UINT_MAX);
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}
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flash_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
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return 0;
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}
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DEVICE_DEFINE(quark_flash, CONFIG_SOC_FLASH_QMSI_DEV_NAME, quark_flash_init,
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flash_qmsi_device_ctrl, FLASH_CONTEXT, NULL, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, (void *)&flash_qmsi_api);
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