95 lines
2.0 KiB
C
95 lines
2.0 KiB
C
/* nrf51-pm.c Power Management for nrf51 chip */
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/*
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* Copyright (c) 2016 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr.h>
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#include <gpio.h>
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#include <uart.h>
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#include <errno.h>
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#define BT_DBG_ENABLED IS_ENABLED(CONFIG_BT_DEBUG_HCI_DRIVER)
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#include "common/log.h"
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#define NBLE_SWDIO_PIN 6
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#define NBLE_RESET_PIN NBLE_SWDIO_PIN
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#define NBLE_BTWAKE_PIN 5
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static struct device *nrf51_gpio;
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int nrf51_wakeup(void)
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{
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return gpio_pin_write(nrf51_gpio, NBLE_BTWAKE_PIN, 1);
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}
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int nrf51_allow_sleep(void)
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{
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return gpio_pin_write(nrf51_gpio, NBLE_BTWAKE_PIN, 0);
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}
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int nrf51_init(struct device *dev)
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{
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u8_t c;
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int ret;
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nrf51_gpio = device_get_binding("GPIO_0");
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if (!nrf51_gpio) {
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BT_ERR("Cannot find GPIO_0");
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return -ENODEV;
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}
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ret = gpio_pin_configure(nrf51_gpio, NBLE_RESET_PIN, GPIO_DIR_OUT);
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if (ret) {
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BT_ERR("Error configuring pin %d", NBLE_RESET_PIN);
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return -ENODEV;
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}
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/* Reset hold time is 0.2us (normal) or 100us (SWD debug) */
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ret = gpio_pin_write(nrf51_gpio, NBLE_RESET_PIN, 0);
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if (ret) {
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BT_ERR("Error pin write %d", NBLE_RESET_PIN);
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return -EINVAL;
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}
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/* Drain the fifo */
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while (uart_fifo_read(dev, &c, 1)) {
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continue;
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}
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/**
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* NBLE reset is achieved by asserting low the SWDIO pin.
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* However, the BLE Core chip can be in SWD debug mode,
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* and NRF_POWER->RESET = 0 due to, other constraints: therefore,
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* this reset might not work everytime, especially after
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* flashing or debugging.
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*/
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/* sleep 1ms depending on context */
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k_sleep(1);
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ret = gpio_pin_write(nrf51_gpio, NBLE_RESET_PIN, 1);
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if (ret) {
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BT_ERR("Error pin write %d", NBLE_RESET_PIN);
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return -EINVAL;
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}
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/* Set back GPIO to input to avoid interfering with external debugger */
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ret = gpio_pin_configure(nrf51_gpio, NBLE_RESET_PIN, GPIO_DIR_IN);
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if (ret) {
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BT_ERR("Error configuring pin %d", NBLE_RESET_PIN);
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return -ENODEV;
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}
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ret = gpio_pin_configure(nrf51_gpio, NBLE_BTWAKE_PIN, GPIO_DIR_OUT);
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if (ret) {
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BT_ERR("Error configuring pin %d", NBLE_BTWAKE_PIN);
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return -ENODEV;
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}
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return nrf51_wakeup();
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}
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