zephyr/soc/riscv32
Nathaniel Graff 8b40260283 boards/riscv32: Add support for the HiFive1 Rev B
The HiFive1 Rev B adds the following features to the
original HiFive1:

 - A second UART peripheral 'uart_1'
 - A hardware I2C peripheral 'i2c_0'
 - Segger J-Link OB
 - An ESP32-WROOM attached to the 'spi_1' peripheral bus

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-05-30 16:54:02 -04:00
..
litex-vexriscv soc: riscv32: add LiteX VexRiscV SoC 2019-05-15 12:52:16 -05:00
openisa_rv32m1 linker: Port usage of custom-sections to use Cmake 2019-05-20 22:28:28 -04:00
riscv-privilege boards/riscv32: Add support for the HiFive1 Rev B 2019-05-30 16:54:02 -04:00
CMakeLists.txt license: cleanup: add SPDX Apache-2.0 license identifier 2019-04-07 08:45:22 -04:00