196 lines
5.2 KiB
C
196 lines
5.2 KiB
C
/*
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* Copyright (c) 2021 Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT gd_gd32_exti
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#include <zephyr/device.h>
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#include <zephyr/drivers/interrupt_controller/gd32_exti.h>
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#include <zephyr/sys/__assert.h>
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#include <zephyr/sys/util_macro.h>
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#include <gd32_exti.h>
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/** Unsupported line indicator */
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#define EXTI_NOTSUP 0xFFU
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/** Number of EXTI lines. */
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#define NUM_EXTI_LINES DT_INST_PROP(0, num_lines)
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/** @brief EXTI line ranges hold by a single ISR */
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struct gd32_exti_range {
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/** Start of the range */
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uint8_t min;
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/** End of the range */
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uint8_t max;
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};
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/** @brief EXTI line interrupt callback. */
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struct gd32_cb_data {
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/** Callback function */
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gd32_exti_cb_t cb;
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/** User data. */
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void *user;
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};
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/** EXTI driver data. */
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struct gd32_exti_data {
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/** Array of callbacks. */
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struct gd32_cb_data cbs[NUM_EXTI_LINES];
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};
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#ifdef CONFIG_GPIO_GD32
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static const struct gd32_exti_range line0_range = {0U, 0U};
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static const struct gd32_exti_range line1_range = {1U, 1U};
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static const struct gd32_exti_range line2_range = {2U, 2U};
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static const struct gd32_exti_range line3_range = {3U, 3U};
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static const struct gd32_exti_range line4_range = {4U, 4U};
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static const struct gd32_exti_range line5_9_range = {5U, 9U};
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static const struct gd32_exti_range line10_15_range = {10U, 15U};
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#endif /* CONFIG_GPIO_GD32 */
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/** @brief Obtain line IRQ number if enabled. */
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#define EXTI_LINE_IRQ_COND(enabled, line) \
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COND_CODE_1(enabled, (DT_INST_IRQ_BY_NAME(0, line, irq)), (EXTI_NOTSUP))
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static const uint8_t line2irq[NUM_EXTI_LINES] = {
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EXTI_LINE_IRQ_COND(CONFIG_GPIO_GD32, line0),
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EXTI_LINE_IRQ_COND(CONFIG_GPIO_GD32, line1),
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EXTI_LINE_IRQ_COND(CONFIG_GPIO_GD32, line2),
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EXTI_LINE_IRQ_COND(CONFIG_GPIO_GD32, line3),
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EXTI_LINE_IRQ_COND(CONFIG_GPIO_GD32, line4),
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EXTI_LINE_IRQ_COND(CONFIG_GPIO_GD32, line5_9),
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EXTI_LINE_IRQ_COND(CONFIG_GPIO_GD32, line5_9),
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EXTI_LINE_IRQ_COND(CONFIG_GPIO_GD32, line5_9),
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EXTI_LINE_IRQ_COND(CONFIG_GPIO_GD32, line5_9),
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EXTI_LINE_IRQ_COND(CONFIG_GPIO_GD32, line5_9),
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EXTI_LINE_IRQ_COND(CONFIG_GPIO_GD32, line10_15),
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EXTI_LINE_IRQ_COND(CONFIG_GPIO_GD32, line10_15),
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EXTI_LINE_IRQ_COND(CONFIG_GPIO_GD32, line10_15),
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EXTI_LINE_IRQ_COND(CONFIG_GPIO_GD32, line10_15),
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EXTI_LINE_IRQ_COND(CONFIG_GPIO_GD32, line10_15),
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EXTI_LINE_IRQ_COND(CONFIG_GPIO_GD32, line10_15),
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EXTI_NOTSUP,
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EXTI_NOTSUP,
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EXTI_NOTSUP,
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#ifdef CONFIG_SOC_SERIES_GD32F4XX
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EXTI_NOTSUP,
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EXTI_NOTSUP,
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EXTI_NOTSUP,
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EXTI_NOTSUP,
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#endif /* CONFIG_SOC_SERIES_GD32F4XX */
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};
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__unused static void gd32_exti_isr(const void *isr_data)
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{
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const struct device *dev = DEVICE_DT_INST_GET(0);
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struct gd32_exti_data *data = dev->data;
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const struct gd32_exti_range *range = isr_data;
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for (uint8_t i = range->min; i <= range->max; i++) {
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if ((EXTI_PD & BIT(i)) != 0U) {
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EXTI_PD = BIT(i);
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if (data->cbs[i].cb != NULL) {
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data->cbs[i].cb(i, data->cbs[i].user);
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}
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}
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}
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}
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void gd32_exti_enable(uint8_t line)
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{
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__ASSERT_NO_MSG(line < NUM_EXTI_LINES);
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__ASSERT_NO_MSG(line2irq[line] != EXTI_NOTSUP);
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EXTI_INTEN |= BIT(line);
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irq_enable(line2irq[line]);
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}
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void gd32_exti_disable(uint8_t line)
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{
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__ASSERT_NO_MSG(line < NUM_EXTI_LINES);
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__ASSERT_NO_MSG(line2irq[line] != EXTI_NOTSUP);
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EXTI_INTEN &= ~BIT(line);
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}
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void gd32_exti_trigger(uint8_t line, uint8_t trigger)
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{
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__ASSERT_NO_MSG(line < NUM_EXTI_LINES);
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__ASSERT_NO_MSG(line2irq[line] != EXTI_NOTSUP);
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if ((trigger & GD32_EXTI_TRIG_RISING) != 0U) {
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EXTI_RTEN |= BIT(line);
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} else {
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EXTI_RTEN &= ~BIT(line);
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}
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if ((trigger & GD32_EXTI_TRIG_FALLING) != 0U) {
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EXTI_FTEN |= BIT(line);
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} else {
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EXTI_FTEN &= ~BIT(line);
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}
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}
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int gd32_exti_configure(uint8_t line, gd32_exti_cb_t cb, void *user)
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{
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const struct device *dev = DEVICE_DT_INST_GET(0);
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struct gd32_exti_data *data = dev->data;
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__ASSERT_NO_MSG(line < NUM_EXTI_LINES);
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__ASSERT_NO_MSG(line2irq[line] != EXTI_NOTSUP);
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if ((data->cbs[line].cb != NULL) && (cb != NULL)) {
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return -EALREADY;
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}
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data->cbs[line].cb = cb;
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data->cbs[line].user = user;
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return 0;
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}
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static int gd32_exti_init(const struct device *dev)
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{
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#ifdef CONFIG_GPIO_GD32
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(0, line0, irq),
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DT_INST_IRQ_BY_NAME(0, line0, priority),
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gd32_exti_isr, &line0_range, 0);
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(0, line1, irq),
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DT_INST_IRQ_BY_NAME(0, line1, priority),
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gd32_exti_isr, &line1_range, 0);
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(0, line2, irq),
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DT_INST_IRQ_BY_NAME(0, line2, priority),
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gd32_exti_isr, &line2_range, 0);
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(0, line3, irq),
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DT_INST_IRQ_BY_NAME(0, line3, priority),
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gd32_exti_isr, &line3_range, 0);
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(0, line4, irq),
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DT_INST_IRQ_BY_NAME(0, line4, priority),
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gd32_exti_isr, &line4_range, 0);
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(0, line5_9, irq),
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DT_INST_IRQ_BY_NAME(0, line5_9, priority),
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gd32_exti_isr, &line5_9_range, 0);
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(0, line10_15, irq),
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DT_INST_IRQ_BY_NAME(0, line10_15, priority),
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gd32_exti_isr, &line10_15_range, 0);
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#endif /* CONFIG_GPIO_GD32 */
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return 0;
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}
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static struct gd32_exti_data data;
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DEVICE_DT_INST_DEFINE(0, gd32_exti_init, NULL, &data, NULL, PRE_KERNEL_1,
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CONFIG_INTC_INIT_PRIORITY, NULL);
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