63 lines
2.0 KiB
Plaintext
63 lines
2.0 KiB
Plaintext
# Copyright (c) 2019 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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menuconfig LOAPIC
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bool "LOAPIC"
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depends on X86
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help
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This option selects local APIC as the interrupt controller.
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if LOAPIC
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config LOAPIC_BASE_ADDRESS
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hex "Local APIC Base Address"
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default 0xFEE00000
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help
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This option specifies the base address of the Local APIC device.
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config X2APIC
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bool "Access local APIC in x2APIC mode"
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help
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If your local APIC supports x2APIC mode, turn this on.
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config LOAPIC_SPURIOUS_VECTOR
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bool "Handle LOAPIC spurious interrupts"
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help
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A special situation may occur when a processor raises its task
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priority to be greater than or equal to the level of the
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interrupt for which the processor INTR signal is currently being
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asserted. If at the time the INTA cycle is issued, the
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interrupt that was to be dispensed has become masked (programmed
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by software), the local APIC will deliver a spurious-interrupt
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vector. Dispensing the spurious-interrupt vector does not affect
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the ISR, so the handler for this vector should return without an EOI.
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From x86 manual Volume 3 Section 10.9.
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config LOAPIC_SPURIOUS_VECTOR_ID
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int "LOAPIC spurious vector ID"
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default -1
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depends on LOAPIC_SPURIOUS_VECTOR
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help
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IDT vector to use for spurious LOAPIC interrupts. Note that some
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arches (P6, Pentium) ignore the low 4 bits and fix them at 0xF.
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If this value is left at -1 the last entry in the IDT will be used.
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config IOAPIC
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bool "IO-APIC"
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default y
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help
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This option signifies that the target has an IO-APIC device. This
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capability allows IO-APIC-dependent code to be included.
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config IOAPIC_MASK_RTE
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bool "Mask out RTE entries on boot"
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default y
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depends on IOAPIC
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help
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At boot, mask all IOAPIC RTEs if they may be in an undefined state.
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You don't need this if the RTEs are either all guaranteed to be masked
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when the OS starts up, or a previous boot stage has done some IOAPIC
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configuration that needs to be preserved.
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endif # LOAPIC
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